3 Replies Latest reply on Mar 20, 2013 7:38 AM by shashank.rebbapragada

    FX2LP Communication Problem with FPGA

    sapan.shah

      Hi,

         

      I am using slave FIFO mode of FX2LP. I ma using data width bettween endpoints FIFO and FPGA as 16-bit. My init routine is as following.

         

       

         

      void TD_Init (void)

         

      { // Called once at startup

         

       

         

        REVCTL = 0x01; 

         

        SYNCDELAY;

         

       

         

        CPUCS = 0x12; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT

         

        //FIFOPINPOLAR |= 0x03;

         

       

         

        PINFLAGSAB = 0xE9; // FLAGB - EP6.FULL, FLAGA - EP4.EMPTY

         

        SYNCDELAY;

         

        PINFLAGSCD = 0xF8; // FLAGD - EP8.FULL, FLAGC - EP2.EMPTY

         

        SYNCDELAY;

         

        PORTACFG |= 0x80;

         

        IFCONFIG = 0x63; // External not-inverted clock, output enabled.

         

        //IFCONFIG = 0x73; // External     inverted clock, output enabled.

         

        //IFCONFIG = 0xC3; // Internal 48 MHz clock, output disabled.

         

        SYNCDELAY;

         

       

         

        // EP4 and EP8 are not used in this implementation...

         

                         

         

        EP2CFG = 0xA2;                //out 512 bytes, 2x, bulk

         

        SYNCDELAY;

         

        EP6CFG = 0xE2;                // in 512 bytes, 2x, bulk

         

        SYNCDELAY;

         

        EP4CFG = 0xA2;                //out 512 bytes, 2x, bulk

         

        SYNCDELAY;

         

        EP8CFG = 0xE2;                // in 512 bytes, 2x, bulk

         

        SYNCDELAY;

         

       

         

        // EP1OIN for interrupts.

         

        EP1INCFG = 0xA0; // out 

         

        SYNCDELAY;

         

       

         

        FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions

         

        SYNCDELAY;                    // see TRM section 15.14

         

        FIFORESET = 0x02;             // reset, FIFO 2

         

        SYNCDELAY;                    // 

         

        FIFORESET = 0x04;             // reset, FIFO 4

         

        SYNCDELAY;                    // 

         

        FIFORESET = 0x06;             // reset, FIFO 6

         

        SYNCDELAY;                    // 

         

        FIFORESET = 0x08;             // reset, FIFO 8

         

        SYNCDELAY;                    // 

         

        FIFORESET = 0x00;             // deactivate NAK-ALL

         

        SYNCDELAY;                    // 

         

       

         

        // handle the case where we were already in AUTO mode...

         

        // ...for example: back to back firmware downloads...

         

        EP2FIFOCFG = 0x20;            // OEP2=0, AUTOOUT=0, WORDWIDE=1

         

        SYNCDELAY;

         

        EP4FIFOCFG = 0x20;            // OEP2=0, AUTOOUT=0, WORDWIDE=1

         

        SYNCDELAY;

         

       

         

        OUTPKTEND = 0x82;

         

        SYNCDELAY;

         

        OUTPKTEND = 0x82;

         

        SYNCDELAY;

         

        OUTPKTEND = 0x84;

         

        SYNCDELAY;

         

        OUTPKTEND = 0x84;

         

        SYNCDELAY;

         

       

         

        // core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's

         

        EP2FIFOCFG = 0x31;            // OEP2=0, AUTOOUT=1, WORDWIDE=1

         

        SYNCDELAY;

         

       

         

        EP4FIFOCFG = 0x31;            // OEP2=0, AUTOOUT=1, WORDWIDE=1

         

        SYNCDELAY;

         

       

         

        EP6FIFOCFG = 0x4D;            // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1, INFM = 1

         

        SYNCDELAY;

         

       

         

        EP8FIFOCFG = 0x4D;            // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1, INFM = 1

         

        SYNCDELAY;

         

       

         

        OUTPKTEND = 0x82;

         

        SYNCDELAY;

         

        OUTPKTEND = 0x82;

         

        SYNCDELAY;

         

        OUTPKTEND = 0x84;

         

        SYNCDELAY;

         

        OUTPKTEND = 0x84;

         

        SYNCDELAY;

         

       

         

        // Interrupts setup.

         

        EXIF &= 0x7F; // Clear INT5 flag.

         

        //EIP |= 0x08; // INT5 high priority.

         

        EIE |= 0x08; // Enable INT5 external interrupt.

         

        EA = 1; // Global Enable.

         

        IE |= 0x80;

         

       

         

        // Timer 0 setup

         

        CKCON &= 0xF7; // Timer0 CLKOUT/12 = 48MHz / 12 = 2 MHz; Timer freq: clk/65535 = 30 Hz.

         

        TMOD = (TMOD & 0xF0) | 0x01; // Timer0 mode: 16-bit

         

        TCON |= 0x10; // Enable Timer0

         

      }

         

       

         

      I am not able to get data from endpoint 4 in FPGA. Can you please help me? 

         

       

         

      Thanks and Regards,

         

      Sapan Shah

        • 1. Re: FX2LP Communication Problem with FPGA
          sapan.shah

           Hi All,

             

          Please help me.

             

          Thanks and Regards,

             

          Sapan Shah

          • 2. Re: FX2LP Communication Problem with FPGA
            chris.mcclelland

            You may find FPGALink[1] helpful. I have not yet added support for 16-bit FIFOs[2], but you should be able to get 8-bit FIFOs working on your board pretty easily.

               

            Chris

               

            [1] http://www.makestuff.eu/wordpress/software/fpgalink/

               

            [2] Actually, in my experience the 8-bit FIFOs are capable of ~43MiB/s which comes close to maxing out the available USB HiSpeed bandwidth. Thus, using 16-bit FIFOs will not be faster.

            • 3. Re: FX2LP Communication Problem with FPGA
              shashank.rebbapragada

               Hi Sapan,

                 

               

                 

              The FPGA not being able to read data from EP4 might well be an issue with your FPGA code/config.

                 

              But I did observe some issues with your FX2LP init code:

                 

              -- IFCONFIG = 0x63 : This setting means that you have configured IFCLK pin as both input and output. This is wrong. Please check this again and change it. I believe the value should be 0x43 (if you are using external IFCLK).

                 

              -- The OUTPKTEND statements are not required, and might be causing some issue as well. You have set REVCTL=0x01. This means that when AUTOOUT transitions from 0 to 1, the core automatically arms the out endpoints. You do not need to do it again explicitly in your code. So these statements can be removed.

                 

              -- The FIFORESET statements should be like this:

                 

               

                 

               FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions

                 

                SYNCDELAY;                    // see TRM section 15.14

                 

                FIFORESET = 0x82;             // reset, FIFO 2

                 

                SYNCDELAY;                    // 

                 

                FIFORESET = 0x84;             // reset, FIFO 4

                 

                SYNCDELAY;                    // 

                 

                FIFORESET = 0x86;             // reset, FIFO 6

                 

                SYNCDELAY;                    // 

                 

                FIFORESET = 0x88;             // reset, FIFO 8

                 

                SYNCDELAY;                    // 

                 

                FIFORESET = 0x00;             // deactivate NAK-ALL

                 

                SYNCDELAY;

                 

               

                 

               

                 

              Please make these changes in your firmware and see if your application works fine.

                 

               

                 

               

                 

              Regards

                 

              Shashank