Might be helpful if you post project for forum to look at.
P0.5 - pulse input ; P0.4 - PGA o/p; P0.1 - input(s) to both comparators.
P0.4 & P0.1 are externally short.
The o/p (LED toggling) is seen on a DSO. The interrupt which should have been triggered by the trailing edge of the input (LTH) doesnt happen. Post your suggestions/changes to be incorporated.
the file's attached
Interrupt is generated only on rising edge of the comparator output. You are getting on CompB; this is due to the noise near the threshold. I would suggest to route the comparator outputs to a pin (through DigBuf) and then see the outputs.
There are two ways of doing this, via ISR as you were doing, and
I ran the ISR approach, and had to use single shot scope capture because the
ISR asynch behaviour making a stable scope presentation difficult.
The attached archive is adding two buffers to bring out to pins the COMP outputs,
no ISRs invlved.
1) I commented out, but left in, your ISR code. boot.tpl as well as main.c
2) Added two bufs, routed to pins in PORT1, I have some stuff on my jig already tied to PORT 2
3) Added a DAC to generate a triangle to feed to the COMPs.
4) Ran on PSOCeval1, 29466
So in short I got both approachesd to work. HW approach slighty cleaner as interrupt latency
and asynch response not a factor.
comp.Archive2.zip 415.1 K
One other thought, Hysteresis around a COMP is important, in almost
all environments. Especially where input signals have very low F compo-
nents. This can cause input to hover around Vth and put COMP into
oscillation, which in an ISR environment would be disastrous. As well
its affects on other HW and processes.