9 Replies Latest reply on Mar 22, 2013 6:21 AM by DaKn_263916

# clocks

Iam using 16 bit counter with ext clk ,counter properties---->period is --1,compare value --0,enable-high,interrupt-TC

input                    output

Now i gave              1Hz      it gives      2sec

10Hz                     200msec

100Hz                    20msec

1KHz                    2mSec       like this...........?  why?

Now i want  how much i wil give frequency from ext.clk that much want as ouput ?

which user module i will use? if period is 1

• ###### 1. Re: clocks

Your counter is dividing by 2 with a period set to 1.

Regards, Dana.

• ###### 2. Re: clocks

how can i generate same frequency as input if period is 1?which user module prefer?properties setting for that user module?

• ###### 3. Re: clocks

If you want same output frequency, you can set the period register of "timer" user module to 0 and set the terminal count pulse width to one-half clock cycle.

Can you please let us know why do you want timer to be configured with same output frequency?

• ###### 4. Re: clocks

If you are trying to regurgitate an input, but with DC of 50%, rjvb recommendations

apply. But it is not absolutely necessary to have Tc set at 1/2 clk, as you could use

Tc vs Compare out as the output frequency.

Regards, Dana.

• ###### 5. Re: clocks

• ###### 6. Re: clocks

• ###### 7. Re: clocks

See attached

• ###### 8. Re: clocks

I stand corrected on this, rjvb is correct. It takes a Period = 0 and Tc = 1/2 clock

to produce a 50% /1 waveform. That occurs only on Tc output, compare out is

irrelevant.

Datasheet is a tad misleading in the section of placing Tc at 1 clock, leads one to

believe /1 topic still relevant.

Regards, Dana.

• ###### 9. Re: clocks

The more I read this section, the more confusing it is -

A period value of zero outputs the input source clock shifted by one-half clock cycle, producing a divide-
by-one clock. In the CY8C29/27/24/22/21xxx, CY8C23x33, CYWUSB6953, CY7C64215,
CY8CLED02/04/08/16, CY8CLED03D/04D, CY8CTST110, CY8CTMG110, CY8CTST120,
CY8CTMG120, CY8CTMA120, CY8C21x45, CY8CTMA300, CY8CTMA301, CY8CTMA301D,
CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28xxxdevice families, the terminal count pulse width
must be set to one-half cycle.

Does that mean, since it listed specific parts, Tc had to be set to 1/2, that there are parts that Tc can be 1 clock ?

Regards, Dana.