I found just sync slave fifo can output a clock. In GPIF2 designer seems output a clock when I select the clock setting as "internal" clock source. But in my design, I want output a lower frquency clock to device and receive a higher frequency as a sync reference clock.
GPIF II accepts an interface clock (PCLK) from the external device upto 100MHz.
Or GPIF II can provide a clock upto 100MHz to the external devices.
This can be changed in the GPIF II designer as shown below:
If you want to change the clock value you can do that by changing pibClock.clkDiv value.