For the display you are using, and its color depth, what is the dot clock
Dot clock is 9MHz.
I by no means am an expert in this area. That being said I would
tackle this by backing into it starting with a window of 111 nS to
do anything, eg. the dot clock. On top of that in the window,
a data transfer, there is decision overhead added to the
burden. So do the calculations for required BW then see if you
can match that up to PSOC.
Attached some material that may be of help.
In closing frame buffers in general have been a blessing to designers.
A lot of designs of yore with marginal timing and crippled image processing
fell into the buffer domain and were made into good designs. So much
graphics.lcd.technologies.pdf 450.0 K
Thanks for reply Dana.
You are right. I am using 55ns SRAM as frame buffer. It is too long write cycle to writing data to SRAM between two dotclock edge. Mayby in another desing i try to use 10ns SRAM. It would then be possible to try writing to SRAM like above and GLCD controller component used only for generating TFT signals and screen refreshing.