The previous Xact error is because hardware error, the crysital does not work well. thanks very much.
and I am trying to add UVC header into the data stream by fpga, and I have two questions :
(1) the first is the problem about ISO transfer
I write a FPGA program, by writing known test data into 68013 , the mode is slave fifo ,FPGA as master;
when 68013 EP6 is configured as bulk in , auto in, autoin length is 512 or 1024, and cyconsole can get the right test data;
but when EP6 is configures as ISO in , auto in ,1024 autoin length, by cyconsole , when the length is 1024 or 2048, 4096, the transfer failed. only when in 8192, I can get the test data.
SO would you please tell the difference between ISO mode and bulk mode ,and how to configure ISO mode ,is there anything need to be configured specially such as SOF interrupt?
(2) The second question is about the Pktend pin in slavefifo mode
The 12bytes UVC header needed to be added into the video streams, so I split the frame data into several packet, each packet size is 1024, and the first 12 bytes are header. the last packet size in a frame is smaller than 1024, so I use the Pktend signal to tell 68013 to send the last packet , and i found in the TRM that it should check fifo fullflag before pktend signal is placed , is my understanding right?
is there any difference between UVC payload size and endpoint autoin packet size ?
The limitation that you saw with CyConsole is due to the following reason:
For ISOC transfers on a device operating at High speed, the following constraints apply to this command:
1) The endpoint transfer size must be a multiple of the endpoint's MaxPacketSize * 8.
2) The buffer length parameter (bufLen in the below examples) must also be a multiple of the endpoint's MaxPacketSize *8.
The above 2 constraints apply to all ISOC transfers, regardless of speed, if using a version of CyUSB.sys older than 184.108.40.206.
So, only when you are using CyUSB.sys, this will apply. Thus, for ISOC transfers, the buffer length and the endpoint's transfers size must be a multiple of 8 times the endpoint's MaxPktSize.
Now, about PKTEND pin:
External master (in your case FPGA) checks for Full flag as to understand it has space for moving data from external master, i.e. ti ensure the biffer is available before sending the data. Once the external master sends the short packet, external master should pulse the PKTEND pin, as to commit the packet to the host domain.
As the PKTend signal, do I need to check the endpoint FIFO_full flag before I make a Pktend pulse.
another question, before a new frame start, what can I do in order to tell 68013 to send all previous frame data in the endpoint buffer datas to host . currently I pulsed the PKTend signal, but it seems not work.
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1) No need to check for Fifo full flag before asserting PKTEND signal. But ypu need to monitor the full flag status from the external master (FPGA) before sending the data.
2) I did not understand your concern about sending the previous frame data to host. You may achieve the data transfer as follows:
Whenever a Microframe starts,(which will be intiated by SOF interrupt inside FX2LP firmware), use some GPIO to intimate this to the FPGA. Whnever microframe starts, send the following:
- first packet = 12Bytes + video frame data (1012 bytes) = total 1024 bytes
- second packet (1024bytes of video frame data)
- third packet = (1024bytes of video frame data)
Whenever the video frame is ending or due tp some reason, when FPGA is sending a packet shorter than 1024, you can pulse PKTEND. In all other cases, packet will get AUTO committed as FX2LP will be in Slave AUTO mode. As soon as the FX2LP buffer fills with 1024 bytes of data, it gets auto committed to the host. The host has to keep reading the IN data in time.
You can use IN endpoint as quad buffered, if you do not want EP for any other purpose.
Small typo in previous post..
......Whenever a Microframe starts,(which will be "INDICATED" by SOF interrupt inside FX2LP firmware), use some GPIO to intimate this to the FPGA.
Also, the three packets in a microframe, that I was talking about in the previous post, is with the assumption that the isc transfers is high speed high bandwidth transfers, with 3 packets every microframe.
an Usts C0000b00 , ISO req failed happened when using busing busbound, what does this mean, the polling interval is 125us , 3frames;
Thanks for your response. and i have some further questions here , hope to get your advice.
The UVC defines the video data should be transferred with 12 byte header and then followed by video data per ISO transfer, what i have done is to make sure this happened
The input video frame is 720x480 16bits with an clk of 27Mhz. so one line contains 1440 bytes data and the line time is about 62.9us. so in 125 us ISO interrupt time ,there are two lines. So I think in this 125us period , the 1440*2 bytes data should be transferred to PC, and I configured EP2ISOINPKTS=3, and auto in length is 1024;
I used an GPIO to to tell FPGA every SOF interrupt happened. then FPGA write data into slavefifo with 12 bytes header first , followed by video data , I used the Pktend before the next SOF interrupt to commit the video data that is shorter than 1024bytes. and repeat it again next SOF happen.
but i did not get the right data at the PC side , by using busbound, the first 12data is not the header I inserted, but video data instead.
I thougt it again, After the SOF interrupt told to FPGA by GPIO , FPGA start to write data into slavefifo, but these data is not transferred after 1024 bytes in filled, transfer 1024 bytes needs about 30us ; so there is only 125-30=95us left for data transfer, maybe the time is not enough to transfer 3 packets in 1024 bytes length. but I do not know how to change it.
I configured EP2 as 1024X4 buffered, and ISO 3x1024 per micro frame.
Thanks in advance.
I did not get why the 12bytes header was not being transmitted over USB if FPGA is sending that before the first 1k byte packet. For FX2LP it is just data whether it be 12 byte header/video data. Please check the implementation in FPGA and also hook up a bus analyzer to view the bus traffic between FPGA and FX2LP.
Also, what you meant by "After the SOF interrupt told to FPGA by GPIO , FPGA start to write data into slavefifo, but these data is not transferred after 1024 bytes in filled". If you set AUTOINLEN of the endpoint as 1024, with EP in Auto mode, it should Auto commit after every 1k bytes.
The data process I think is as following:
when SOF interrupt happened( suppose it is at 0us), FPGA start to write data into slavefifo (which is 1k*4 buffered and with an autoin length of 1024) , Suppose the slavefifo is empty when the SOF interrupt happened, and I think the IN transfer started after FPGA write 1024 bytes into slavefifo(and in my system , with a data clk of 27Mhz, it takes about 30us time for FPGA to write these 1024 bytes data) . In other word , at time 30us , FPGA write done 1024 bytes, and USB in transfer begins. so in the first 30us, USB transfer did not happen.
The next SOF interrupt is at 125us, and ISO packet is 3, so I think 3 ISO packets should be transferred from time 30us to 125us, and the time is not enough. but I really do not familiar with how the usb ISO transfer did . would you please give some explanation on ISO transfer of 68013;
As to the FPGA side , everytime SOF starts , 12 bytes header is wrote first by FPGA , and then video data is wrote.
what I want to implement is UVC spec tells SOF packet with following DATA2, DATA 1, DATA 0; Is there other possible ways to implement this by 68013 ? I though about using autoin=0, FPGA write data before SOF interrupt so when SOF interrupt happened, data in ready in the endpoint buffer and by setting Fireware( but I do not know how) , transfer immediately happen. In this way the synchronizaiton control seems not easy.
The UVC spec defines that every ISO transfer should be start with 12 bytes header and then video data following.
so what I want to implement is what the UVC spec defined.
currently I use two ways to implement this:
(1) I insert 12bytes header into the video stream to form a packet size of 1024 bytes.
the stream after inserting is like this:
12 bytes header+ 1012 video data;
12 bytes header+ 1012 video data;
the length of the last packet in the frame may be less than 1012, then I use PKtend to send the last packet;
and the slavefifo is configured as 1K*4 bufferd , and autoin;
the busbound results shows that in most case, an ISO transfer is start with 12 bytes header I inserted, but sometime not . but Idid not find the root cause
(2) I referred to the advice you give. In the fireware , I set an GPIO very SOF interrupt, when FPGA get that the status of the GPIO changed , it begin to write data into slavefifo with 12 header first , then video data,, bofore the next SOF interrupt, I use the PKTEND signal to tell to Fireware to send all the previous data.
and the slavefifo is configured as 1K*4 bufferd , and autoin; ISO packet length is 3;
the busbound results shows in most case , the ISO transfer is not begin with the header I inserted, and I thougt the reason in the previous text;
would you please help anylise the root cause of the two method?
or Is there other possible ways to add UVC header by FPGA so 68013 could send the data as UVC spec said?
ISO transfer in FX2LP is just like any other ISO transfer. Also, one more thing even though first 1k packet of data is available for transfer only after 30us in a microframe, the 1k packet transfer will happen at USB 2.0 speed across the USB bus and not at 27mhz. So, after 90us even your third packet would be available and still you have (125-90)us left for transferring the third packet in the microframe. Theoretically it seems possible, just observe the USB traffic and see how it takes place in real. USB traffic analyzer like CATC/Ellysis can be a good help in this regard, than Bus hound.
Now, if you are considering (AUTOIN = 0) manual mode for implementing UVC, I don't think it would be feasible to implement ISO transfers, as 8051 in the data path will make it tremendously slow. Such an implementation will not be possible.
So what is the final solution?
What we've implemented is that the FPGA has a task to add the header every 1024Bytes. Then add EOF header at last packet.
The FX2LP is configured for Slave FIFO, AUTOIN =1, EP2AUTOINLENH:L=1024, ISO EP2 Buffer 4 x 1024, EP2ISOINPKTS = 0x82 (2 transactions / microframe).
It works well but not very reliable.
I want to add the header from 8051 but I don't know how :p
How can do this process:
(1) - Add header in 12 first bytes. EP2FIFOBUF=0x0C; EP2FIFOBUF=0x02; EP2FIFOBUF=0x80......EP2FIFOBUF=0
(2)- Let FPGA append video data
My question >
When I add manually the header (12bytes), how can I ensure that the FPGA will not overwrite my header previously added? in over hand the EP2FIFOBCH:L is auto-incremented after action (1) ?
In order to insert header from FX2LP, you will have to configure FX2LP in manual mode. However, adding header using FX2LP will be time consuming, since you have to shift the data in the endpoint to make room for 12 bytes header. What is your expected bandwidth?
How are you implementing the same using FPGA now? Are you using Isoc transfers? If so, are you notifying the SOF information to FPGA using GPIO or something?
If you are using Slave FIFO manual mode, then the 8051 CPU would need to keep checking for data in TD_Poll() and then add/modify few bytes and then commit the buffer. All this would cause some processing delay, and as a result you might not be able to achieve the 24Mbytes/sec max throughput. If your throughput requirement is lesser than this, then it might be possible, but it would need to be tested anyway.