This posting is for info only . . . hoping it might help someone
We implemented a 2 bit synchronous slave FIFO with auto DMA. We had an issue where I would send a packet from the host and the FPGA master would read 233 words(32 bit) and then the flag would get deasserted and would assert every 60 cycles for a duration of 1 read. Also, every other word (32b) would be missing.
FPGA designer was always assrting RD# and just uning the flag to tell him when we had valid data. I asked him to start deasserting RD# on empty and that fixed the problem. The FX3 slave FIFO timing diagrams do not really show you what to do with the control signlal when the flag toggles from asserted-unasserted-asserted. He basically repeated the sequnse he does when the flag is first asserted (see flag, assert RD#, wait 2 PCLKs for data).
Hope this helps someone. I did not see this anywhere in the forum so you guys must be all smarter than us!!!!!!!!!!!!
Thanks for posting this. It should be helpful to other users who might run into this issue.