The logic to be implemented is Out= High+(Out*low)
I try to write this as a truth table:
C1 C2 out
0 0 0
0 1 0
1 0 0
1 1 1
Is this right? Then you need a AND gate - but this will result in what you described: when C1 goes low so does the output.
Or do want to have a time-sensitive logic? Then you need a DFF: connect C1 to its Clock-Input, a logic 1 to the D input, and the inverted C2 to the reset input.
That way, the rising flank of C1 will set the output to 1, and it will stay there even if C1 goes low again. When C2 goes low, it will reset the DFF so the output goes low againb.
That circuit works when implemented using discrete logic files because of propagation delays but inside PSOC it might be optimised out diferently.
You need to use a FF to store the previous state.
I cannot look at any of these images, I always get an error message:
The request has exceeded the allowable time limit Tag: CFQUERY
How should Comp_2 behave: when it gioes low, the output goes low. But when it goes high again, should the output still stay low?
I would implement it this way:
(which is what I explained above). Feeding back the out signal to the enable input will only ensure that the DFF triggers once, because after that the clock input will be ignored).
Seems like a bit of a guessing game going on.
Some questions -
1) Comparators looking at same signal ? Or two different signals ?
2) Can you provide a state diagram :? Your logic expression confers
simple combinatorial logic, no delay elements.....This would also give forum
init state as well as reset state/conditions.
3) Timing diagram ?
4) Analog signal origin, type, bandwidth....
Oh! Good idea, Smart and simple, No need an additional clock.
@dana: the logic expression uses 'out' both as input and output, so there is clearly delay involved...
PSOC73's pictures are spot-on, unfortunatelly they require a clock signal.
HLI's solution is great, but what happens at power on?
UDB's FF's are initialized to a 0 value. Therefore, there might a malfuntion if at power on comp1 output is high and the FF output will still be low. Logic should be added to ensure it is initialised high if comp1 is high.
I think the easiest way would be to build a custom UDB component, a couple of always@(posenge A or B) would do the trick
I stand corrected, the delays are implicit, not explicit. Not only that I missed
schematic posted, and delay discussion in original description. Time for a vacation.
Looking at top level schematic originally posted, any reason not to do entire
design with a A/D and some code to effect thresholds and "levels" detected.
Which rasies what are the signal properties ? Again what is function being sought
Don't forget, if you can do it with A/D and code, the A/D's input buffer
can amp by a factor up to 8, eg. eliminate the PGA in the design as well.