1 2 3 Previous Next 29 Replies Latest reply on May 13, 2013 12:02 PM by nikhil.naik

    Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA

    alessandro.angelino

       Hi,

         

      I have just read the AN61345 by Rama Sai Krishna V, which explains and provides examples for a complete configuration of a Host + FX2LP + FPGA system. I saw in the Document History that there used to be a version with details about the Virtex5. 

         

      I am currently trying to develop a system like the one described in that application note on a Avnet Virtex5 board, and was wondering if that version of the document is still available.

         

      Thank you so much.

         

      Regards,

         

      Alessandro Angelino

        • 2. Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA
          nikhil.naik

           The older projects had a timing  voilation and using internal IFCLK in FX2LP. So the projects had been updated.

             

          The new projects use external IFCLK on FXLP.

             

          If you still want the files, you can mail nikl@cypress.com or rskv@cypress.com

          1 of 1 people found this helpful
          • 3. Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA
            nikhil.naik

             Check this post for info on the latest projects:

               

            http://www.cypress.com/?app=forum&id=167&rID=78668

            1 of 1 people found this helpful
            • 4. Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA
              alessandro.angelino

              Hi, thank you for your help.

                 

               

                 

              The project I'm working on is based on a pre-existing design which worked with the serial port. Now I would like to upgrade it to a USB connection, using the CyAPI library on the host side.

                 

               

                 

              I just need quite a little amount of data to be sent from the FPGA to the PC and other data on the way back - all data is provided by the FPGA itself, so no particular computation is needed by the USB controller. I saw the AN61345 and realized that the slave mode is probably the most suitable for my design, but this is the very first time I'm approaching USB, so I was looking for something very close to my configuration in order to have more material to start from.

                 

               

                 

              I will also read the link you posted, and maybe try to send an email for those older versions of the application note.

                 

               

                 

              Do you have any suggestion for the implementation of such a system on a Virtex5 Avnet board? Thank you!

              • 5. Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA
                alessandro.angelino

                In particular, my problem is related to the pin assignment in the .ucf file, which I don't know how to adapt to my board.

                • 6. Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA
                  nikhil.naik

                   Pin assignment depends on your hardware.

                     

                  Either you already have a hardware and then you decide which pins you want to use and put it down in your ucf.

                     

                  Or first decide your pin assignment, create an ucf and then design your hardware accordingly.

                     

                  Let us know details on your interface so that one of us can assist you in deciding the pin assignment.

                  1 of 1 people found this helpful
                  • 7. Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA
                    alessandro.angelino

                    Yes, I'd really appreciate someone's help about this topic.

                       

                     

                       

                    The hardware I'm working on is an Avnet board, the V5LX50, with a Xilinx XC5VLX50-FF676 FPGA and a Cypress CY7C68013A-100AC USB Microcontroller. I would like to modify the ucf file given with the design example related to the AN61345 in order to make it compatible with the board I'm using... but actually I don't know where to start from!

                       

                     

                       

                    Thank you very much in advance!

                    • 8. Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA
                      nikhil.naik

                       alemrto

                         

                      In the loopback example (path: \AN61345 - Source files for FPGA code and FX2LP Firmware\001-61345\FPGA Source Code_Verilog\Loopback\fx2lp_loopback_proj\) you can find a ucf file with the following content:

                         

                       

                         

                      NET "clk"  LOC = "K14" |IOSTANDARD = LVCMOS33 ;

                         

                       

                         

                      NET "clk_out"  LOC = "J14" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ; 

                         

                       

                         

                      NET "fdata<0>"  LOC = "C16" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ; 

                         

                      NET "fdata<1>"  LOC = "C15" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "fdata<2>"  LOC = "D16" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "fdata<3>"  LOC = "D14" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "fdata<4>"  LOC = "E13" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "fdata<5>"  LOC = "E12" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "fdata<6>"  LOC = "F16" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "fdata<7>"  LOC = "F15" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "fdata<8>"  LOC = "P10" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "fdata<9>"  LOC = "N12" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "fdata<10>"  LOC = "P12" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "fdata<11>"  LOC = "N5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "fdata<12>"  LOC = "P5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "fdata<13>"  LOC = "L8" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "fdata<14>"  LOC = "L7" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "fdata<15>"  LOC = "R5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                       

                         

                      NET "faddr<0>"  LOC = "T5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ; # PA4

                         

                      NET "faddr<1>"  LOC = "N11" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ; # PA5

                         

                      NET "slrd"  LOC = "K11" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "slwr"  LOC = "J11" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "sloe"  LOC = "T3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ; # PA2

                         

                      NET "flaga"  LOC = "F12" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                      NET "flagd"  LOC = "T10" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                         

                       

                         

                      NET "done"  LOC = "G11" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                      1 of 1 people found this helpful
                      • 9. Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA
                        nikhil.naik

                         To explain the signals:

                           

                        "clk" is the IFCLK (input clock for Slave fifo interface; can be internal/external); on ZTEX board this is connected to "K14" pin of FPGA.

                           

                        In you case you will to find which pin of FPGA is IFCLK of Fx2lp connected to and replace K14 with the pin.

                           

                        Make the similar changes in the verilog code

                        1 of 1 people found this helpful
                        • 10. Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA
                          nikhil.naik

                           Similarly for 

                             

                          clk_out: clock out from FX2LP; this is input clock to FPGA PLL; a phase shift clock is generated using clk_out of FX2LP and given to IFCLK of Fx2LP

                             

                          fdata: slave fifo data; can be 8/16 bit data;

                             

                          faddr<0>, <1>: is slave address

                             

                          slrd, slwr and sloe are general slave read, write and enable signals

                             

                          Flag a/d: flags to indicate fifo status

                             

                          done: is high when FPGA configuration is done; in Fx2lp firmware this bit is polled for (check code in TD_Poll function); when this bit is high the IFCLK is changed from internal to external in FX2LP firmware (because if IFCLK is supposed to be External, the IFCLK should already be present when IFCLK is configured as external)

                          1 of 1 people found this helpful
                          • 11. Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA
                            nikhil.naik

                             for all of the above signals of FX2LP you need to find the corresponding connections on FPGA on your board and make the corresponding changes in ucf and verilog code.

                               

                            Please let me know if the information helped.

                            1 of 1 people found this helpful
                            • 12. Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA
                              prajith.cheerakkoda

                               Hi,

                                 

                               UCF file is shown below

                                 

                               

                                 

                              NET "clk" TNM_NET = "clk";

                                 

                              NET "clk"  LOC = "K14" |IOSTANDARD = LVCMOS33 ;

                                 

                               

                                 

                              NET "clk_out"  LOC = "J14" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ; 

                                 

                               

                                 

                              NET "fdata<0>"  LOC = "C16" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ; 

                                 

                              NET "fdata<1>"  LOC = "C15" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "fdata<2>"  LOC = "D16" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "fdata<3>"  LOC = "D14" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "fdata<4>"  LOC = "E13" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "fdata<5>"  LOC = "E12" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "fdata<6>"  LOC = "F16" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "fdata<7>"  LOC = "F15" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "fdata<8>"  LOC = "P10" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "fdata<9>"  LOC = "N12" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "fdata<10>"  LOC = "P12" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "fdata<11>"  LOC = "N5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "fdata<12>"  LOC = "P5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "fdata<13>"  LOC = "L8" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "fdata<14>"  LOC = "L7" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "fdata<15>"  LOC = "R5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                               

                                 

                              NET "faddr<0>"  LOC = "T5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ; # PA4

                                 

                              NET "faddr<1>"  LOC = "N11" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ; # PA5

                                 

                              NET "slrd"  LOC = "K11" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "slwr"  LOC = "J11" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "sloe"  LOC = "T3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ; # PA2

                                 

                              NET "flaga"  LOC = "F12" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "flagd"  LOC = "T10" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "pkt_end"  LOC = "T11" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "sync"  LOC = "G12" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              NET "done"  LOC = "G11" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              You can map the pins as per your hardware connection by changing LOC, Eg if pin F12 of FPGA is connected to Flagd, for this UCF can be changed as

                                 

                              NET "flagd"  LOC = "F12" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;

                                 

                              Regards

                                 

                              Prajith

                              1 of 1 people found this helpful
                              • 13. Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA
                                alessandro.angelino

                                That was really helpful, thank you!

                                   

                                 

                                   

                                I created my own UCF file following your suggestions. Actually there were some problems with my target device, because some of the signals were multiplexed and needed other signals in order to be used.

                                   

                                 

                                   

                                I still have some doubts:

                                   

                                 

                                   

                                1) PRJI posted a sample version of the UCF file with the "sync" signal, but I don't have it in my design example. Shall I add it?

                                   

                                 

                                   

                                2) I had to make the following modifications to the VHDL code of the design example to adapt it to the Virtex5:

                                   

                                ODDR_2 was substituted with ODDR

                                   

                                DCM_SP was substituted with DCM_ADV

                                   

                                and after synthesization i have the following warnings:

                                   

                                 

                                   

                                CODE:

                                   

                                dout_next <= data_array(conv_integer(read_index(7 downto 0))); 

                                   

                                WARNING:

                                   

                                Index value(s) does not match array range, simulation mismatch.

                                   

                                 

                                   

                                CODE:

                                   

                                process(current_loop_back_state, flagd) begin
                                        if((current_loop_back_state = loop_back_write) and (flagd = '1') and (fifo_empty = '0')) then
                                            slwr_n <= '0';
                                        else
                                            slwr_n <= '1';
                                        end if;
                                    end process;

                                   

                                WARNING:

                                   

                                One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: fifo_empty. (The same warning is displayed for the LoopBack mode state machine combo)

                                   

                                 

                                   

                                Is it a problem?

                                   

                                 

                                   

                                3) I tried the design with the USB Control Center: it successfully executes the bulk out transfer, and when I try the bulk in transfer, I only receive the "ODD" part of data correctly:

                                   

                                 

                                   

                                INPUT:

                                   

                                BULK OUT transfer
                                0000 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
                                0010 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
                                0020 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
                                0030 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
                                0040 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
                                0050 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
                                0060 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F
                                0070 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
                                0080 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F
                                0090 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F
                                00A0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF
                                00B0 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF
                                00C0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF
                                00D0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
                                00E0 E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF
                                00F0 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
                                0100 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
                                0110 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
                                0120 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
                                0130 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
                                0140 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
                                0150 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
                                0160 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F
                                0170 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
                                0180 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F
                                0190 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F
                                01A0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF
                                01B0 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF
                                01C0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF
                                01D0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
                                01E0 E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF
                                01F0 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
                                BULK OUT transfer completed

                                   

                                 

                                   

                                OUTPUT:

                                   

                                BULK IN transfer
                                0000 FE 01 FE 03 FE 05 FE 07 FE 09 FE 0B FE 0D FE 0F
                                0010 FE 11 FE 13 FE 15 FE 17 FE 19 FE 1B FE 1D FE 1F
                                0020 FE 21 FE 23 FE 25 FE 27 FE 29 FE 2B FE 2D FE 2F
                                0030 FE 31 FE 33 FE 35 FE 37 FE 39 FE 3B FE 3D FE 3F
                                0040 FE 41 FE 43 FE 45 FE 47 FE 49 FE 4B FE 4D FE 4F
                                0050 FE 51 FE 53 FE 55 FE 57 FE 59 FE 5B FE 5D FE 5F
                                0060 FE 61 FE 63 FE 65 FE 67 FE 69 FE 6B FE 6D FE 6F
                                0070 FE 71 FE 73 FE 75 FE 77 FE 79 FE 7B FE 7D FE 7F
                                0080 FE 81 FE 83 FE 85 FE 87 FE 89 FE 8B FE 8D FE 8F
                                0090 FE 91 FE 93 FE 95 FE 97 FE 99 FE 9B FE 9D FE 9F
                                00A0 FE A1 FE A3 FE A5 FE A7 FE A9 FE AB FE AD FE AF
                                00B0 FE B1 FE B3 FE B5 FE B7 FE B9 FE BB FE BD FE BF
                                00C0 FE C1 FE C3 FE C5 FE C7 FE C9 FE CB FE CD FE CF
                                00D0 FE D1 FE D3 FE D5 FE D7 FE D9 FE DB FE DD FE DF
                                00E0 FE E1 FE E3 FE E5 FE E7 FE E9 FE EB FE ED FE EF
                                00F0 FE F1 FE F3 FE F5 FE F7 FE F9 FE FB FE FD FE FF
                                0100 FE 01 FE 03 FE 05 FE 07 FE 09 FE 0B FE 0D FE 0F
                                0110 FE 11 FE 13 FE 15 FE 17 FE 19 FE 1B FE 1D FE 1F
                                0120 FE 21 FE 23 FE 25 FE 27 FE 29 FE 2B FE 2D FE 2F
                                0130 FE 31 FE 33 FE 35 FE 37 FE 39 FE 3B FE 3D FE 3F
                                0140 FE 41 FE 43 FE 45 FE 47 FE 49 FE 4B FE 4D FE 4F
                                0150 FE 51 FE 53 FE 55 FE 57 FE 59 FE 5B FE 5D FE 5F
                                0160 FE 61 FE 63 FE 65 FE 67 FE 69 FE 6B FE 6D FE 6F
                                0170 FE 71 FE 73 FE 75 FE 77 FE 79 FE 7B FE 7D FE 7F
                                0180 FE 81 FE 83 FE 85 FE 87 FE 89 FE 8B FE 8D FE 8F
                                0190 FE 91 FE 93 FE 95 FE 97 FE 99 FE 9B FE 9D FE 9F
                                01A0 FE A1 FE A3 FE A5 FE A7 FE A9 FE AB FE AD FE AF
                                01B0 FE B1 FE B3 FE B5 FE B7 FE B9 FE BB FE BD FE BF
                                01C0 FE C1 FE C3 FE C5 FE C7 FE C9 FE CB FE CD FE CF
                                01D0 FE D1 FE D3 FE D5 FE D7 FE D9 FE DB FE DD FE DF
                                01E0 FE E1 FE E3 FE E5 FE E7 FE E9 FE EB FE ED FE EF
                                01F0 FE F1 FE F3 FE F5 FE F7 FE F9 FE FB FE FD FE FF
                                BULK IN transfer completed

                                   

                                 

                                   

                                is this something related to hardware? I think this behavior is quite strange, it seems like only a part of the data, systematically, is being read, while the other is given as simple repetition of the last (even) hex received.

                                   

                                 

                                   

                                Thank you very much again for your help.

                                • 14. Re: Questions about AN61345 - Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA
                                  nikhil.naik

                                   0000 FE 01 FE 03 FE 05 FE 07 FE 09 FE 0B FE 0D FE 0F

                                     

                                  0010 FE 11 FE 13 FE 15 FE 17 FE 19 FE 1B FE 1D FE 1F
                                  0020 FE 21 FE 23 FE 25 FE 27 FE 29 FE 2B FE 2D FE 2F
                                  0030 FE 31 FE 33 FE 35 FE 37 FE 39 FE 3B FE 3D FE 3F
                                  0040 FE 41 FE 43 FE 45 FE 47 FE 49 FE 4B FE 4D FE 4F
                                  0050 FE 51 FE 53 FE 55 FE 57 FE 59 FE 5B FE 5D FE 5F
                                  0060 FE 61 FE 63 FE 65 FE 67 FE 69 FE 6B FE 6D FE 6F

                                     

                                   

                                     

                                  The input data is like this because FGPA is sending out data as soon as it is configured.

                                     

                                  So solve this issue, you will need a sync signal from FX2LP

                                  1 of 1 people found this helpful
                                  1 2 3 Previous Next