5 Replies Latest reply on May 16, 2013 3:12 AM by sun.dazhi

    GPIF cannot work at 100MHz clock

    dp.li
              I encounter an problem when about using GPIF at 100MHz in synchronous-slave-fifo-write mode. The scenario is as below: the pclk is 100MHz, SLWR write 16KB to GPIF, and switch the FIFO ADDR. But after SLWR sending the next 16KB, the flagb will be valid, and keep valid all the time. Then SLWR could not write data any more, so did GPIF.   
        • 1. Re: GPIF cannot work at 100MHz clock
          dp.li
                  I did some other experiments and found that when SLWR write no more than 320Bytes then insert an interval, the GPIF could work continuously. The screenshot of timing is in attachment. Please tell me how GPIF could work at 100MHz continously. Your early reply will highly appreciated!   
          • 2. Re: GPIF cannot work at 100MHz clock
            rama.sai.krishna.vakkantula

            Hi,

               

            What is the device connected to GPIF II port of FX3?

               

            Is it an FPGA?. Did you look at the projects that are attached to the following application note:

               

            http://www.cypress.com/?rID=51581

               

            It look like you are able to fill the 16KB of buffer allocated to that DMA channel and then I am not sure whether you are reading that buffer from the USB side. Please share more details of your application.

               

            Thanks,

               

            sai krishna.

            • 3. Re: GPIF cannot work at 100MHz clock
              dp.li
                      It's FPGA connected to GPIF II port of FX3. The DMA should read the data once the buffer filled to 16KB. It seems the data was not be moved out. Don't konw why. The scenario works well at 90MHz.   
              • 4. Re: GPIF cannot work at 100MHz clock
                rama.sai.krishna.vakkantula

                 Hi,     

                 

                   

                Please check whether you have this piece of code in main function of FX3 firmware. If not, please add it.     

                 

                   

                CyU3PSysClockConfig_t clkCfg = {    

                 

                   

                                        CyTrue,    

                 

                   

                                        2, 2, 2,    

                 

                   

                                        CyFalse,    

                 

                   

                                        CY_U3P_SYS_CLK    

                 

                   

                    };    

                 

                   

                    

                          

                   

                    /* Initialize the device */    

                 

                   

                    status = CyU3PDeviceInit (&clkCfg);    

                 

                   

                    if (status != CY_U3P_SUCCESS)    

                 

                   

                    {    

                 

                   

                        goto handle_fatal_error;    

                 

                   

                    }    

                 

                   

                Thanks,    

                 

                   

                sai krishna.    

                • 5. Re: GPIF cannot work at 100MHz clock
                  sun.dazhi
                          thank you for your answer!! I try this in my project, but there are different conclusions in different hosts. In intel & Renesas hosts,it runs very well, however we encounter babble detect in Asmedia host, please tell me how to resolve it, waiting for your answer!!