1 Reply Latest reply on May 21, 2013 4:47 PM by user_14586677

    CE5212 Designer Sinewave LUT Project Errors

    user_14586677

      A couple of issues that need addressing -

         

       

         

      1) Global properties, the OpAmp Bias and Ananlog Buffer properties both were set to low power,

         

      so sine wave distorted. Those should be set to high power.

         

       

         

      2) Because the A Buffer is not R-R, its exacerbates the distortion of the DAC output when close to either

         

      rail. Maybe a note should be added to ap note covering this.

         

       

         

      3) As an exercise, to eliminate the distortion in 2), I added a PGA, set its G < 1, to get waveform away

         

      from rails, and woulnd up with a highly distorted waveform, ? Not sure why.

         

       

         

      Note A Buffer was only loaded with 10M scope probe in all observations, maybe in case of 2) high load

         

      might actually improve output distortion.....?

         

       

         

      PSOC Designer 5.4

         

       

         

      Regards, Dana.