1 2 Previous Next 22 Replies Latest reply on Jun 9, 2013 12:19 AM by nikhil.naik

    FX2LP FPGA interface

    jon.bean

       I am trying to get an FPGA interface working on a FX2LP. I have used the application note AN61345 Spartan 6 design, just changing the FPGA pins to match my own. If I use the USB control centre to send some bytes to the FX2LP it reports that it worked fine. However when I try to read them back it gives the following error.

         

      BULK IN transfer failed with Error Code:997

         

      Can someone tell me what this means? I am a bit surprised that the example design would not just work out of the box.

         

      Thanks

         

      Jon

        • 1. Re: FX2LP FPGA interface
          prajith.cheerakkoda

           Hi,

             

          Are you using ZTEX module? Does streamer example work ? How many OUT transfers could you perform? 

             

          Could you please probe the interface lines and let me know your observations? 

             

          -PRJI

          • 2. Re: FX2LP FPGA interface
            jon.bean

             I managed to get it going. There was some setting that were not correct.

            • 4. Re: FX2LP FPGA interface
              robert.dorn

              I have the same problem.

                 

              Which settings?

                 

              I'm using a Zetex module.

              • 5. Re: FX2LP FPGA interface
                jon.bean

                 I'm not using a Ztex module. If you post your descriptors I may be able to help.

                   

                Jon

                • 6. Re: FX2LP FPGA interface
                  prajith.cheerakkoda

                  Hi, 

                     

                  Does streamer example work ? How many OUT transfers could you perform? 

                     

                  Could you please probe the interface lines and let me know your observations? 

                     

                  -PRJI

                  • 7. Re: FX2LP FPGA interface
                    nikhil.naik

                     Hi Richie72

                       

                    Is it a Spartan6 Ztex module you are using?

                       

                     

                       

                    Thanks

                       

                    Nikhil

                    • 8. Re: FX2LP FPGA interface
                      robert.dorn

                      Yes, I'm using the Spartan6 Zetex 1.11 module.

                         

                      I'm trying to run the examples of the AN61345 application notes, without any changes.

                         

                      @prji: I can execute Bulk Out Transfer 4 times.

                      • 9. Re: FX2LP FPGA interface
                        robert.dorn

                        The streamer example don't work.

                        • 10. Re: FX2LP FPGA interface
                          prajith.cheerakkoda

                           Hi,

                             

                           Since EP2 OUT is 512 x 4 you will be able to do 2K of OUT transfer, these packets go to OUT buffer of FX2LP not to FPGA. It seems your FPGA is not configured properly or not getting proper voltage on control or data pins. Check Flag(FlagD and FlagA) status after each Out transfer, it should change after 4th transfer in case of dataloopback example. As the data transfer in the Streamer example is unidirectional I would suggest you to start debugging with this example, it would be easier to isolate issue. Probe on data lines to ensure FPGA has been configured properly and is pumping data to FX2LP.

                             

                          -PRJI

                          • 11. Re: FX2LP FPGA interface
                            nikhil.naik

                             Richie

                               

                            How are you loading the FPGA bit stream?

                               

                            Are you first loading the FX2LP image and then loading the FPGA bit-stream (through JTAG) as mentioned in the App. Note?

                               

                            Thanks

                               

                            Nikhil

                            • 12. Re: FX2LP FPGA interface
                              nikhil.naik

                               Richie

                                 

                              Please check out the "variants" mentioned in the following site:

                                 

                              http://www.ztex.de/usb-fpga-1/usb-fpga-1.11.e.html

                                 

                              Which variant are you using?

                                 

                              Thanks

                                 

                              Nikhil

                              • 13. Re: FX2LP FPGA interface
                                robert.dorn

                                I'm using the Ztex Module 1.11c with the LX25  with a Experimental Board 1.2. 

                                   

                                          

                                   

                                I’m trying to run the examples (Loop Back, Streamin) like you described it in the AN61345 paper.

                                   

                                Everything works fine, but the BULK IN transfer fails with the following error:

                                   

                                                BULK IN transfer

                                   

                                BULK IN transfer failed with Error Code:997

                                   

                                 What does that error means?

                                   

                                 

                                   

                                I have registered the ZETEX VID and PID in the CyUSB.inf.

                                   

                                Then downloaded the slave.hex to the RAM via USB.

                                   

                                After that I have downloaded the bit-streams with the XILINX Platform Cable USB II and the impact tool.

                                   

                                 

                                   

                                BULK OUT works fine, but the BULK IN transfer always fails.

                                   

                                In the CyConsole the FX2 appears as SLAVE FX2, is that ok?

                                   

                                Endpoints 2 and 6 are configured:

                                   

                                 

                                   

                                                                               <ENDPOINT>

                                   

                                                                                               Type="BULK"

                                   

                                                                                               Direction="OUT"

                                   

                                                                                               Address="02h"

                                   

                                                                                               Attributes="02h"

                                   

                                                                                               MaxPktSize="512"

                                   

                                                                                               DescriptorType="5"

                                   

                                                                                               DescriptorLength="7"

                                   

                                                                                               Interval="0"

                                   

                                                                               </ENDPOINT>

                                   

                                 

                                   

                                                                               <ENDPOINT>

                                   

                                                                                               Type="BULK"

                                   

                                                                                               Direction="IN"

                                   

                                                                                               Address="86h"

                                   

                                                                                               Attributes="02h"

                                   

                                                                                               MaxPktSize="512"

                                   

                                                                                               DescriptorType="5"

                                   

                                                                                               DescriptorLength="7"

                                   

                                                                                               Interval="0"

                                   

                                                                               </ENDPOINT>

                                   

                                 

                                   

                                In the USB Data Streamer application there is no choice for the endpoint configuration.

                                • 14. Re: FX2LP FPGA interface
                                  prajith.cheerakkoda

                                   Hi,

                                     

                                   

                                     
                                       The error code 997 refers I/O pending for the overlapped to      http://msdn.microsoft.com/en-us/library/windows/desktop/ms681388(v=vs.85).aspx        
                                     
                                      
                                     
                                     
                                      As I told you earlier the next step should be control and data line probing. Since FX2LP enumerates and performs OUT transfers successfully I suspect FPGA. Please probe the FLAG lines and confirm FPGA is getting EP6 empty flag in the streamer example.   
                                     
                                      
                                     
                                     
                                      -PRJI   
                                     
                                      
                                     
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