Zero Detect behaviour in datapath

[HuEl_264296]

I am creating a 16-bit datapath component which can create different flashing patterns on an LED. The D0 and A0 registers are loaded with the bit pattern, and the component shifts the bits out of the A0 registers, into the LED until A0 is zero, then re-loads the bit pattern into A0 from D0.

   

However, I'm a little confused about the behaviour of the ZDET line. I assumed that the ZDET line would go high for one whole clock cycle until A0 was re-loaded from D0. I.E. like this:

       

CLK      A0        SO    ZDET   Reload --- ------------   --    ----   ------  0: 010100000000  1: 101000000000  2: 010000000000   HI  3: 100000000000  4: 000000000000   HI     HI  5: 010100000000                Reload  6: 101000000000  7: 010000000000   HI  8: 100000000000

   

 Instead, ZDET seems to go high for less than 1us (whereas the clock has a period of 100ms).

       

What is the correct behaviour for the ZDET line?

[HuEl_264296]

 On further examination, it seems that those very short pulses on the ZDET line that you can see on my attached image were just crosstalk from the LED line. 

       

Which actually makes this even stranger! Why can't I see any signal at all on the ZDET line?

       

Attached is the Verilog code for my component.

[HuEl_264296]

 The reason you're not seeing a signal from ZDET is because you have a failed solder joint on your PSoC chip.

[HuEl_264296]

 Oh, cool, thanks. It works now.