2 Replies Latest reply on Jun 14, 2013 3:04 PM by JoMe_264151

    Instantiate a clock inside a verilog component


      I am creating a Verilog component which requires a clock. I would like this to be an internal clock, so that the user doesn't need to concern themselves with it.




      I have seen some components (eg PWM) which have the option of an internal clock. This is implemented by using a schematic component containing the clock plus another verilog component.




      Is it possible instead to simply instantiate a clock within the Verilog?