AFAIK you need the external clock. This is because PSoC needs to allocate a clock resource for that (e.g. a divider), and this is something separate from the UDB. So you will need a schematic component for that.
There is no VeriLog instruction that creates a clock and sets its frequency, Easiest would be to connect a clock to your component and use that a s a macro or wrap it into a schematic component.