Please help me in understanding your problem correctly.
1.) FLAG_A => OUT RDY
2.) FLAG_B => OUT WATERMARK
3.) FLAG_C => IN RDY
4.) FLAG_D => IN WATERMARK
At your side, you don't see any issue for the following data path:
FPGA --> FX3 IN endpoint --> PC
You are saying that you have problem with the OUT data transfers:
PC --> FX3 OUT endpoint --> FPGA.
As per my understanding you are facing probelm in the above mentioned data path. Please let me know if my understanding is correct.
If yes, then how are you giving the PKTEND# in this direction?. Also please let me know the number of bytes that you are transferring.