Do you want to count signal with a frequency of up to 48MHz? When I understand the data sheet (and the architecture TRM) right, in counter mode the clock is the operating clock, and the count input will be sampled by this clock (though it is nowhere explicitely explained how it works exactly).
In all other modes you should be able to run the component with 48MHz (or the system clock at most). But the TRM (http://www.cypress.com/?docID=43515 ) talks about a prescaler for this component, maybe you need to check for that?
the prescaler works corectly, prescaler divides internaly the input clock (1-128). My problem is with maximum operating frequency, for "clock" and "count" inputs.
The TCPWM can be used w/o a count input, just a clock input.
48 Mhz probably unrouted internal max clock rate. Consider filing a tech case at -
"Create a Case"
When you have a data signal, and want to use it as a clock, you either connect it to a clock input. Or you use a sync component to synchronize it to the bus clock. The latter way is preferred because it allows Creator to know all timing details.
The last option would be to attach the data signal to an internal pin and specify this pin as clock (in the design wide resources) .
Aargh! Wrong thread for the last post :(
My idea was to check whether a prescaler would be active and reduce the clock frequency (I don't think this should happen, but who knows...)
Otherwise: can you test whether a PWM can run with full frequency?
Does a counter run with full clock, but just with lower frequency on the count input?