1 Reply Latest reply on Jun 17, 2013 4:40 AM by rama.sai.krishna.vakkantula

    FX2LP EP2FIFO FF problem

    mark.allen

      I think I posted in the wrong forum previously, so I am going to repost my problem here. I have constructed an interface using an FPGA to drive the EP2FIFO. I am using the EP2FIFO FF as FLAGB, and the FPGA uses the flag to tell it when to stop sending data. Data is requested using EP8, and that part is working fine. However, EP2FIFO FF is going high after 64 bytes, which made me think the EP was working in low speed mode. However, I can see, using UCView, that the max packet size for the EP2 is 512 bytes, and the connection is high speed. I have to believe I m making an obvious mistake, but I do not see it. Here is my EPSetup:

         

       

         

      void EPSetup(void)
      {

      //    HistctrlReset(1);



          REVCTL=0x1;     // Enhanced Packet Handling

          // set the slave FIFO interface to 48MHz
          IFCONFIG = 0x03;    // IFCLKSRC=0   , FIFOs executes on external clk source
                              // xMHz=0       , 48MHz internal clk rate
                              // IFCLKOE=0    , Don't drive IFCLK pin signal at 48MHz
                              // IFCLKPOL=0   , Don't invert IFCLK pin signal from internal clk
                              // ASYNC=0      , master samples asynchronous
                              // GSTATE=0     , Don't drive GPIF states out on PORTE[2:0], debug WF
                              // IFCFG[1:0]=11, FX2 in slave FIFO mode
          SYNCDELAY;                   

          // set up registers for EndPoint communication

          // Registers which require a synchronization delay, see section 15.14
          // FIFORESET        FIFOPINPOLAR
          // INPKTEND         OUTPKTEND
          // EPxBCH:L         REVCTL
          // GPIFTCB3         GPIFTCB2
          // GPIFTCB1         GPIFTCB0
          // EPxFIFOPFH:L     EPxAUTOINLENH:L
          // EPxFIFOCFG       EPxGPIFFLGSEL
          // PINFLAGSxx       EPxFIFOIRQ
          // EPxFIFOIE        GPIFIRQ
          // GPIFIE           GPIFADRH:L
          // UDMACRCH:L       EPxGPIFTRIG
          // GPIFTRIG
         
          // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
          //      ...these have been replaced by GPIFTC[B3:B0] registers
         
          // default: all endpoints have their VALID bit set
          // default: TYPE1 = 1 and TYPE0 = 0 --> BULK 
          // default: EP2 and EP4 DIR bits are 0 (OUT direction)
          // default: EP6 and EP8 DIR bits are 1 (IN direction)
          // default: EP2, EP4, EP6, and EP8 are double buffered

          // reset EP FIFOs
          // Reset all FIFOs
          SYNCDELAY;
          FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions
          SYNCDELAY;                    // see TRM section 15.14

          EP8FIFOCFG=0x01;    //Use WORDWIDE
          SYNCDELAY;
          EP2FIFOCFG=0x05;    // use ZEROLENIN,WORDWIDE
          SYNCDELAY;

          FIFORESET = 0x02;             // reset, FIFO 2
          SYNCDELAY;                    //
          FIFORESET = 0x04;             // reset, FIFO 4
          SYNCDELAY;                    //
          FIFORESET = 0x06;             // reset, FIFO 6
          SYNCDELAY;                    //
          FIFORESET = 0x08;             // reset, FIFO 8
          SYNCDELAY;                    //
          FIFORESET = 0x00;             // deactivate NAK-ALL
          SYNCDELAY;


          SYNCDELAY;
          EP1OUTCFG=0xA0; //Bit 7 - Valid=1;
                          //Bit 6 - NC 0
                          //Bit [5..4] - TYPE=BULK(0x2);
                          //Bit 3 - Size=512(0);
                          //Bit 2 - 0
                          //Bit [1..0] - 0

          SYNCDELAY;                   
          EP1INCFG=0xA0;  //Bit 7 - Valid=1;
                          //Bit 6 - NC 0
                          //Bit [5..4] - TYPE=BULK(0x2);
                          //Bit 3 - Size=512(0);
                          //Bit 2 - 0
                          //Bit [1..0] - 0
          EP1OUTBC=0;
          SYNCDELAY;
             
          // Set up endpoints
          // Bit      Task
          //  7       VALID - turns on EP if 1
          //  6       DIR - 0=out;1=in
          //  5..4    TYPE - 0=invalid;1=ISO;2=bulk;3=interrupt      
          //  3       SIZE - 0=512;1=1024
          //  2       NC
          //  1..0    BUF - 0=quad;1=invalid;2=double;3=triple
          // EP1 is bidirectional


          SYNCDELAY;                   
          EP2CFG = 0xE2;  //Bit 7 - Valid=1;
                          //Bit 6 - DIR - 0=out;1=in
                          //Bit [5..4] - TYPE=BULK(0x2);
                          //Bit 3 - Size=512(0);
                          //Bit 2 - 0
                          //Bit [1..0] - BUF=DOUBLE(0x2)


          SYNCDELAY;                   
          EP8CFG = 0xA0;  //Bit 7 - Valid=1;
                          //Bit 6 - DIR=OUT(0);
                          //Bit [5..4] - TYPE=BULK(0x2);
                          //Bit 3 - Size=512(0);
                          //Bit 2 - 0
                          //Bit [1..0] - BUF=DOUBLE(0x2)
          SYNCDELAY;

          // Unused EPs still take up memory if they are not configured LAST.
          // FIFO memory is first come, first allocated.
          SYNCDELAY;                   
          EP4CFG = 0x2;   // disable; only double buffered

          SYNCDELAY;                    
          EP6CFG = 0x2;   // disable; only double buffered

          // Set up FIFO Operations
          // Bit      Task
          //  7       NC
          //  6       INEARLY - if 1, causes IN flags to appear one clock cycle earlier
          //  5       OUTEARLY  - if 1, causes OUT flags to appear one clock early
          //  4       AUTOOUT - if 1, data is auto-committed to USB (only used for OUT FIFO)
          //  3       AUTOIN  -   if 1, uses PKTLEN register
          //  2       ZEROLENIN - if 1, a PKTEND commits a zero-length packet
          //  1       NC
          //  0       WORDWIDE - if 1, data is 16 bits wide
      //    EP8FIFOCFG=0x11;    //Use AUTOOUT,WORDWIDE

          EP8FIFOCFG=0x11;    //Use AUTOOUT,WORDWIDE
          SYNCDELAY;
          EP2FIFOCFG=0x0D;    // use AUTOIN,ZEROLENIN,WORDWIDE
          SYNCDELAY;

          // set up autoin length to be 512. if we are not high speed, we can only send
          // a maximum of 64 byte packets (see Descriptor). The AUTOINLEN must be the same
          // as the max packet in the descriptor.
          if(EZUSB_HIGHSPEED())
          {
              EP2AUTOINLENH=0x02;
              SYNCDELAY;
              EP2AUTOINLENL=0x00;
              SYNCDELAY;

          }
          else
          {
              EP2AUTOINLENH=0x00;
              SYNCDELAY;
              EP2AUTOINLENL=0x40;
              SYNCDELAY;
          }

          // EP2 FF = 0xC  EP8EF= 0xB
      //    PINFLAGSAB=0xC8;   
      PINFLAGSAB=0xCB;   
          SYNCDELAY;
      //    PINFLAGSCD=0xFB;   
      PINFLAGSCD=0xBB;  
          SYNCDELAY;
          PORTACFG |= 0x80;             // FLAGD, set alt. func. of PA7 pin
          SYNCDELAY;
          FIFOPINPOLAR=0x3; // we want all flags to be active high
          SYNCDELAY;


          // out endpoints do not come up armed
         // since the defaults are double buffered we must force 2 packets
          SYNCDELAY;                    //
          OUTPKTEND=0x88;
          SYNCDELAY;
          OUTPKTEND=0x88;



          // enable dual autopointer feature
          AUTOPTRSETUP |= 0x01;
         
      }