I am assuming that you are using the project files which are attached to AN65974.
I am assuming that you connected a FPGA to GPIF II of FX3.
Zero length packet will be asserted in following cases:
· If FPGA does not have any data and if it want to send that to PC then it will assert PKTEND# signal without writing any data. Then that will generate a Zero length packet.
· If you are receiving the Zero length packet where you are not supposed to, that might be due to the action that you are doing in the GPIF II state machine. You should be doing IN_DATA action along with the COMMIT action. If you are just using the COMMIT action then it will generate an additional Zero length packet.
if you mean that when i use the commit action , the zore-length data must be produced ?
I would like to know whether you are getting the Zero Length packet where you are not supposed to.
If yes, please attach your GPIF II project here.
I will take a look at it and suggest you how to avoid that.