Did you try setting the "Active clock edge" field in GPIFII designer to Negative? This is effectively like inverting the PCLK before sending it out to your slave. So your slave will operate on rising edge and FX3 will operate on falling edge. I believe this might solve your issue.
Hi Shashank, The point is not clock edge polarity, but the sampling time. The GPIF will sample data immediately when CS and RD are active. But there is delay when slave detected active read operation and output data to bus. For example, CS and RD become 0 at t0, then GPIF will sample data at t0, however, the slave detected read at t0 and output data at t1. Regards, Rover