This sounds very strange and althoug I've done some designs with I2C I've never seen something similar.
I'm afraid you have to break down your project to the pure I2C-communication.
Ah... try to use I2C_SlaveClearReadStatus() instead
Thanks for the reply.
Turns out it was the slew rate on the microchip PIC that the PSoC was trying to chat to. In the logic analyzer it looked great, but on the oscilloscope I soon saw a problem. The PSoC wasn't actually seeing the stop sequence. What looked nice and square on the logic analyzer were actually well rounded peaks on the 'scope. The pull ups are 4.7K and cannot be changed at this time.
Anyway, what I did was switch them round - the PSoC is now master, the PIC is slave, so the PSoC is driving the bus and it works great. I've even been able to get better throughput. Clock stretching works a treat also! Ka-ching!
This particular board has loads of I2C on it - 4 Audio processors, 2 NVRAM and the PIC all on I2C buses. The PIC does Ethernet offloading for me. Since I2C SLAVE on the pic has to be interrupt driven it even makes the ethernet throughput a bit better - we are not blocked while doing I2C writes and reads for as long as we were in master mode.
In case you want/need to swap master and slave again, you might use a I2C bus buffer to get better signals. E.g. one from Linear Technologies: http://parametric.linear.com/i2c_and_smbus_bus_buffers_and_accelerators
Thanks thats a good bit of advice.
In this case the board already exists (in their 1,000's) so a change to the PCB was not possible.