What to watch for:
- do you use an output buffer for the VDAC?
- To which drive mode is it set?
No buffer on the PSoC side, goes directly to a pin configured as Analog.
Range: 0 - 4.080
Data Source: CPU
Strobe mode: Register Write
Are you using the same version of components?
Try your software with 2.2 NOT 2.2SP1, see if there is any difference. I did notice some changes between 2.2SP1 and 2.2.
To Hli's point -
Both output ranges have 255 equal steps. The VDAC8 is implemented by driving the output of
the current DAC through resistors and obtaining a voltage output. Because no buffer is used, any
DC current drawn from the DAC affects the output level. Therefore, in this mode any load
connected to the output should be capacitive.
The output R of the VDAC -
Do you use the same hardware just different code from different creator?
I mean SAME PIECE of hardware. Not same circuitry.
You do not need to compare your both settings to each other, just swap the projects on your boards and you can see any differences in behaveour.
I am a little bit confused about your circuitry: you are really driving an LED with the VDAC? I'm not sure what you like to perform with that, but the LED will start at ~1.7V to glow (depending on LED colour) and the drive current the VDAC delivers will not be enough to have any linearity in brightness.
Usually you use a PWM-based driver to controll an LED's brightness, like the PRISM usermodule.
Look at the table Dana provided. The VDAC has an output resistance of 16K (in the 4V range). This forms a voltage divider with the load your are attaching to the output. When using a 20k load, this basically halves the output voltage - which is exactly what you are observing.
So the solution is to add a voltage follower as output buffer. This should reduce the output impedance.
Nick, just to confirm that you are not using the same hardware as the other hardware enginner. is this correct? I GOT the small text box again!!!!!!!1
We are using the same hardware, swapping the programs. The hardware engineer brought me the board, demonstrated his code, gave me the board, I loaded my code and I get the behavior, so there has to be a reason.
My code is compiled in 2.0, then the latest greatest 2.2 SP1. The hardware engineer is in Creator 2.1.
The HW engineer did find the statement in the data sheet about that the load should be purely capacitive.
It certainly makes sense that I'm making a voltage divider between the 4.84 and ground. Doing the math I see that I would get 2.15V.
Thanks for the help.
Do you mean that the program from the other engineer did not thave the problem, but your software has the problem, And you are using the same hardware and internal hardware of the PSOC. JUST use different creator. If that is the case. Did you try to use the creator he used to build your code and see if that changes?
Adding a voltage follower helps...importance of an opamp does not come from any change in voltage, but from the input and output impedances of the op-amp. The input impedance of the op-amp is very high, meaning that the input of the op-amp does not load down the source and draws only minimal current from it.
also i have recently used it... the noise level difference reduced to arnd 100mv (i was getn a 1v o/p)!!!!!
I passed your comment on to the hardware engineer. I think it's worth a try and should put the problem into one camp or the other. Just finding the time to fit it in is the only issue.
The thing is, the results from my code are as expected per the data sheet. It looks like for some reason, there is no voltage divider in his configuration.