1 Reply Latest reply on Jul 24, 2013 3:41 PM by derek.kozel

    FX3 GPIF Underrun and Overrun in Synchronous Slave FIFO interface

              Hello, I'm working on a project with an FX3 connected to a Xilinx FPGA. We are using a 16 bit Synchronous Slave FIFO interface with the FPGA being the master. We are using our own FPGA code. We're using the following application note as our reference. Designing with the EZ-USB FX3 Slave FIFO Interface http://www.cypress.com/?docID=44080 AN65974 Rev. H We are using a dedicated USB endpoint for transfers and using DMA to link it to the GPIF threads. The DMA buffers are 512 bytes large and there are two per channel /* Create a DMA MANUAL channel for U2P transfer. */ dmaCfg.size = 512; dmaCfg.count = 2; dmaCfg.dmaMode = CY_U3P_DMA_MODE_BYTE; dmaCfg.prodSckId = CY_FX_PRODUCER_USB_SOCKET; dmaCfg.consSckId = CY_FX_CONSUMER_PPORT_SOCKET; We are doing block transfers of 512 bytes. Flag A is dedicated to thread 0 and Flag B is dedicated to thread 3. I added the gpif_error_cb callback function from the application note and found that we are encountering two CYU3P_PIB_ERR_THR0_RD_UNDERRUN errors when the FPGA reads from the FX3 and two CYU3P_PIB_ERR_THR3_WR_OVERRUN errors when it writes to the FX3. What is unclear from the documentation is exactly what these errors mean. Is the FPGA (master) trying to read two 16 bit words too many? And trying to write two 16 bit words too many? Given that we are using dedicated flags I don't believe we should be encountering multicycle latency problems. Is that correct? There a period after the SLWR or SLRD lines are asserted during which data is not yet transferred (two cycles stated on page 5), do we need to deassert SLRD before actually receiving 256 16 bit words? We aren't currently using watermarks for either transaction, I understand you can use that, but it doesn't seem to be required so we'd like to understand the exact transaction before trying that. Thanks!