2 Replies Latest reply on Aug 2, 2013 4:47 AM by babu.borusu

    qdrll+ memory controlle rwith sram

    babu.borusu

       Hi,

         

                     I want to know the number of the cycles till CQ/CQ# is stable.In the xilinx IP-Core it is given that 2048 cycles for the clock stable .

         

      PART no :CY7C25632KV18.

         

      Thanking you