1 Reply Latest reply on Aug 2, 2013 8:40 PM by userc_40792

    Clock for ADC

      Dear All,


      While reading the appnote AN77900, PSoC® 3 and PSoC 5LP Low-power Modes and Power Reduction Techniques, in page 5 is stated, or I understand, that the clock value of the Master Clock needs to be higher than the value for the ADC.


      I was testing something that shouldn't work but I don't get an error (see the image attached). You can see that I've deliberately lowered the clock... How can this not show a warning?





        • 1. Re: Clock for ADC
                  Hi sergiakalorth,   
          Clock editor of Creator still has a small bug.   
          For example, when nominal clock frequency is much different with desire frequency,   
          It been not warning.   
          Workspace explore / result TAB / ...timing.html (Static Timing Analysis)   
          is provide othe static report. Is it something help for you?