I have been trying to design a 16 bit Datapath for simple subtraction routine. It was pretty simple with an 8 bit datapath but somehow I can not figure out how to build a 16 bit one. I guess the problem is with status register signals from the Verilog module that indicate that calculation has been completed. Can someone here look at it and identify the exact problem? I am attaching the bundle. I will be grateful for a response.