7 Replies Latest reply on Aug 18, 2017 2:14 PM by kaiyu.lin

    DMA buffers full signal

    kaiyu.lin
              Hi! I'm testing the streaming in configuration as mentioned in AN65974, although I modified the VHDL in order to send an increasing counter toward FX3. The data that I get in Control Center whenever I press "Transfer data in" are not linked in the sense that the last number of the previous transfer isn't equal to the first number minus 1 of the next transfer. I need a full memory signal from DMA in order to avoid overwriting data and another signal that notice me that data has been read from control center. How can I do that? Thank you!   
        • 1. Re: DMA buffers full signal
          rama.sai.krishna.vakkantula

           Hi,     

           

             

          This is taken care in the project files of AN65974.     

           

             

          We are using Flag A to identify whether Thread 0 is ready to accept the data and Flag B to know the full condition of the DMA buffer.     

           

             

          You can follow the same way.     

           

             

          If you are already using the project files of AN65974, please check whether you are using the latest files that are available with that application note.     

           

             

          Thanks,     

           

             

          Sai Krishna.     

           

          • 2. Re: DMA buffers full signal
            kaiyu.lin
                    Hi! Thank you for helping. What does exactly happen when i press the "transfer data in" button? Does it read all DMA buffers from the first to the last and then reset them all? Or does it read them and change the flag b to empty memory state? Thank you!   
            • 3. Re: DMA buffers full signal
              rama.sai.krishna.vakkantula

               Hi,

                 

              "Transfer Data In" button just reads 'x' bytes of data from the USB device. 'x' is the value that you enter in the space next to "Bytes to transfer".

                 

              DMA controller present in FX3 takes care of finding a free buffer when the already allocated buffer is filled and changing the flags based on the buffer status.

                 

              Please let me know if you have any more questions on this topic.

                 

              Thanks,

                 

              Sai Krishna.

              • 4. Re: DMA buffers full signal
                kaiyu.lin

                Hi!

                   

                 

                   

                from AN65974 i can see that when fx3 is programmed with streaming firmware, it creates two DMA channels:

                   

                 

                   

                1) P2U: 16kB for USB 3.0 and the buffer count is 8

                   

                2) U2P: 16kB for USB 3.0 and the buffer count is 4

                   

                 

                   

                I need clarification on the following questions:

                   

                 

                   

                1) I always read 16kB from "Transfer data in", so the entire buffer stack is read at once. 

                   

                    Then I suppose that the DMA controller changes the flag A to 1 and the FPGA transfer another 16kB into the stack. With flag B on 1 (stack full condition), FX3 waits untill I press again "Transfer data in" and it starts all over again. Is it right?    

                   

                 

                   

                2) My project need only one way data transfer, from FPGA toward FX3. Can I re-allocate the 16kB of U2P in order to have 32kB for P2U?

                   

                 

                   

                3) What is the buffer count?

                   

                 

                   

                Thank you!!

                • 5. Re: DMA buffers full signal
                  rama.sai.krishna.vakkantula
                          Hi, Here are the answers to your questions: 1) I always read 16kB from "Transfer data in", so the entire buffer stack is read at once. Then I suppose that the DMA controller changes the flag A to 1 and the FPGA transfer another 16kB into the stack. With flag B on 1 (stack full condition), FX3 waits untill I press again "Transfer data in" and it starts all over again. Is it right? For P2U data path, Buffer size is 16KB and you have 8 of them. So the total buffer allocated for this data path is 8x16KB = 128KB. This FLAGA changes its value (from 1 to 0) when one of these 8 buffers is filled and trying to get the next buffer. This delay is called buffer switching delay and FPGA should not write any data during this period and this can be done with the help of FLAGA. As soon as it finds a next buffer the FLAGA value changes back to 1, indicating that buffer is available. In this manner, you should be able to write 128KB of data with out reading from the Control Center. If you read a 16KB of data using Control Center then that FlagA changes its value to indicate the availability of one buffer. And this process continues... 2) My project need only one way data transfer, from FPGA toward FX3. Can I re-allocate the 16kB of U2P in order to have 32kB for P2U? Yes. You can do that. If you are using the part which has 512 KB then this is not a problem. You can create a DMA channel with 32KB x 4 = 128KB buffering. 3) What is the buffer count? You can go for 6 as well if that satisfies your application requirement. With the 512KB RAM part, I have created a DMA channel with total buffering of around 252KB. (Total RAM - Total code size) can be allocated for DMA buffers. Thanks, Sai Krishna.   
                  • 6. Re: DMA buffers full signal
                    kaiyu.lin
                            Thank you! Your answer was very helpful. I need to ask you one more thing: Flag B: when it is high it means that the memory is full and i should not write, but in the state machine drawing of streaming in, the writing state is triggered by flag B that changes from 0 to 1. My VHDL also writes toward FX3 when both flag A and flag B are high. Is flag B active low? ps. in wich pdf can I find specifications on how to re-allocate buffers? Thank you.   
                    • 7. Re: DMA buffers full signal
                      kaiyu.lin
                              Sorry Sai Krishna, ignore my previous post. I read again the AN65974 and the flags role are more clear to me now. i. FLAGA: Full flag dedicated to thread0 ii. FLAGB: Partial flag with watermark value 6, dedicated to thread0 I am supposing that we need FLAGB just because there is a 3-cycle latency from the write cycle that causes the buffer to become full to the time that the FLAGA gets asserted low. So, in order to not loss any data during that 3-cycle, we use FLAGB. Is it right? Watermark question: "When writing from an external master to the Sync Slave FIFO: The number of data words that may be written AFTER the clock edge at which the partial FLAG is sampled low = watermark x (32/bus width) – 4" In the streaming firmware the watermark is set by default to 6, that means i can still write during the first 2-cycle latency of FLAGB. Is it right? Thank you so much!