2 Replies Latest reply on Sep 25, 2014 11:41 PM by user_14586677
      • 1. Re: Programming PSoC 5LP PLD registers from main.c code
        vignesh.thangavel

         Hi!

           

        I have been trying to configure PLD0 of UDB2 as a 2:4 decoder from the main.c code after instantiating a single LUT with two inputs and 4 outputs and throwing in 4 digitial output pins, 2 digital input pins and connecting them to the LUT with wires in the schematic. I configured the truth table of the LUt in the schematic to give one for all cases. When I built it, I noticed in the .rpt file under results tab, that UDB(3,4) had been configured to acheive this functionality of the LUT described above. After reading the registers TRM for PSoC 5LP, I identified the following registers to configure the logic function of PLD0 of UDB(3,4) - which according to the application note on advanced DMA topics, corresponds to UDB2 :

           

        B0_P1_U0_PLD_IT0 (to take input 0), B0_P1_U0_PLD_IT1(to take input 1), B0_P1_U0_PLD_ORT0(to produce output 0) B0_P1_U0_PLD_ORT1 (to produce output 1), B0_P1_U0_PLD_ORT2 (to produce output 2), B0_P1_U0_PLD_ORT3 (to produce output 3), B0_P1_U0_MC-CFG_BYPASS (to configure macrocells to produce combinational output). 

           

        I guess these are the only registers necessary to configure the logic function of PLD0 as a 2:4 decoder. I used the following code to configure it in main.c:

           

               CyDelay(1000);

           

                CY_SET_REG32(CYREG_B0_P1_U0_PLD_IT0, 0x000C0003); //bits 19,18 are true inputs, bits 0,1 are complement inputs for first 4 PTs for input0

           

        CY_SET_REG32(CYREG_B0_P1_U0_PLD_IT1, 0x000A0005); //bits 19,17 are true inputs, bits 0,2 are complement inputs for first 4 PTs for input1

           

        CY_SET_REG16(CYREG_B0_P1_U0_PLD_ORT0, 0x0001); //bit 0 to set first PT as output of OR line 0

           

        CY_SET_REG16(CYREG_B0_P1_U0_PLD_ORT1, 0x0002); //bit 1 to set second PT as output of OR line 1

           

        CY_SET_REG16(CYREG_B0_P1_U0_PLD_ORT2, 0x0004); //bit 2 to set second PT as output of OR line 2

           

        CY_SET_REG16(CYREG_B0_P1_U0_PLD_ORT3, 0x0008); //bit 3 to set second PT as output of OR line 3

           

                CY_SET_REG16(CYREG_B0_P0_U0_MC_CFG_BYPASS, 0x0055); //setting bits of all 4 macrocells to give combinational output 

           

        I connected wires from the output pins to the LEDs on board to see the outputs and also wires from input pins to 5V and GND on the breadboard to change the inputs and see how outputs vary with it. For 1 second,all four LEDs were glowing and then the code I had wirtten configured those registers -this I could verify by the new outputs observed. However, for 2 of the 4 cases I got the right output, while for the other cases it didn't give any output unfortunately. I tried verifying the values I wrote to the registers and they agree very well with the TRMs and documents I have read so far. I haven't configured the MC_CFG_XORFB and MC_CFG_CEN_CONST registers as I didn't feel it was necessary to do so. I don't know if there are any other registers I need to configure.

           

         

           

        Does anyone know what registers need to be configured to achieve the output described above? Need urgent help with this as my project is due by next Monday. Your help is deeply appreciated.

           

        Thanks!

        • 2. Re: Programming PSoC 5LP PLD registers from main.c code
          user_14586677

          Post your project so forum can examine.

             

           

             

              

             

                    

             

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           Regards, Dana.