I found the solution.
I falsely believed the EcoDiv was the divider for the SYSCLK, but is it for the HFCLK.
And since the SYSCLK divider was set to 2 in the settings, the clock got divided further down to 1.5 MHz.
So i added the line:
/* Change Prescaler for SYSCLK - set to 1, since ECO is already divided by 8*/
After setting ECO as HFCLK source.