4 Replies Latest reply on Jul 12, 2017 7:29 AM by psberro_2592021

    PSOC 5 power monitor Issue

    psberro_2592021

      Hi ,

         

      I have a design with the PSOC 5 , that is used to monitor the board power supply voltage levels.

         

      we have about 10 power supplies ,  9 of them are reading the exact voltage but i have an issue with the 3.3V reading that is connected to the PSOC using a voltage divider resistor network ( 50K + 50K ) .

         

      when i measure the voltage on the PSOC using a fluke i read ~1.65V which is OK since 1.65*2=3.3V . but the SOC reports a higher voltage , around 3.45V.

         

      I have connected an osciloscope to the analog input and saw that above the nominal 1.65V , at a frequency of about 500hz there is a small repetitive ramp in the voltage that appear only after the voltage divider and is not seen  at the power supply output. this ramp explains why the psoc reports a higher voltage after averaging

         

      to make sure that the interference is related to the SOC , ive compiled a version disconnecting this sense signal from the power monitor and indeed the interference disappeared.

         

      My theory is that the ramp i saw is caused because the internal A/D is muxed between my other inputs and the parazitic capacitance "Remembers" the old voltage and then samples a higher voltage ( since my sense line is connected through 50K resistor , the current is not sufficient to make the transition transparent ) .

         

      I am trying to find a fix without changing the voltage devider to lower resistive values , i was thinking to make the sample rate much slower so the voltage can be stable before the sampling is made but i cant find this option on the configuration GUI .

         

      Any Ideas?

         

       

         

      Thanks!