Anonymous
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Jul 19, 2017
11:07 PM
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Jul 19, 2017
11:07 PM
Hi there,
I got problem with interfacing Cypress SPI Master running on PSOC 5 Cortex-M3 MCU with Avalon-ST SPI Core running on MAX 10 FPGA Altera.
Any Suggests,
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PSoC 5LP
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Jul 20, 2017
02:34 AM
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Jul 20, 2017
02:34 AM
Welcome in the forum.
A bit bare information to make suggestions. Can you please post your complete project so that we all can have a look at all of your settings. To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
Bob