Reason for GPIO Configuration in GPIF Master code

[Anonymous]

I am using the GPIF master example (http://www.cypress.com/?docID=45301) to get my project going.  In looking at the code, I see the following code that confifgures a lot of hte GPIO pins.  I am trying to understand if this is for GPIF or just system configuration.  How do I find out the reason for all of the below GPIO settings for GPIO50, 51, 52, 57 and the others?

               

/******************/
/* Configure GPIO */
/******************/

   

/* Init the GPIO module */
gpioClock.fastClkDiv = 2;
gpioClock.slowClkDiv = 0;
gpioClock.simpleDiv = CY_U3P_GPIO_SIMPLE_DIV_BY_2;
gpioClock.clkSrc = CY_U3P_SYS_CLK;
gpioClock.halfDiv = 0;

   

/* Initialize Gpio interface */
apiRetStatus = CyU3PGpioInit(&gpioClock, NULL);
if (apiRetStatus != 0)
{
/* Error Handling */
CyU3PDebugPrint (4, "GPIO Init failed, Error Code = %d\n",apiRetStatus);
CyFxAppErrorHandler(apiRetStatus);
}
apiRetStatus = CyU3PDeviceGpioOverride (23, CyTrue);
apiRetStatus = CyU3PDeviceGpioOverride (25, CyTrue);
apiRetStatus = CyU3PDeviceGpioOverride (26, CyTrue);
apiRetStatus = CyU3PDeviceGpioOverride (27, CyTrue);
apiRetStatus = CyU3PDeviceGpioOverride (50, CyTrue);
apiRetStatus = CyU3PDeviceGpioOverride (51, CyTrue);
apiRetStatus = CyU3PDeviceGpioOverride (52, CyTrue);
apiRetStatus = CyU3PDeviceGpioOverride (57, CyTrue);

   

gpioConfig.outValue = CyFalse;
gpioConfig.inputEn = CyFalse;
gpioConfig.driveLowEn = CyTrue;
gpioConfig.driveHighEn = CyTrue;
gpioConfig.intrMode = CY_U3P_GPIO_NO_INTR;

   

apiRetStatus = CyU3PGpioSetSimpleConfig(23, &gpioConfig);
apiRetStatus = CyU3PGpioSetSimpleConfig(25, &gpioConfig);
apiRetStatus = CyU3PGpioSetSimpleConfig(26, &gpioConfig);
apiRetStatus = CyU3PGpioSetSimpleConfig(27, &gpioConfig);
apiRetStatus = CyU3PGpioSetSimpleConfig(50, &gpioConfig);
apiRetStatus = CyU3PGpioSetSimpleConfig(51, &gpioConfig);
apiRetStatus = CyU3PGpioSetSimpleConfig(52, &gpioConfig);
apiRetStatus = CyU3PGpioSetSimpleConfig(57, &gpioConfig);

   

CyU3PGpioSimpleSetValue (23, 1);
CyU3PGpioSimpleSetValue (25, 0);
CyU3PGpioSimpleSetValue (26, 1);
CyU3PGpioSimpleSetValue (27, 0);
CyU3PGpioSimpleSetValue (50, 1);
CyU3PGpioSimpleSetValue (51, 0);
CyU3PGpioSimpleSetValue (52, 1);
CyU3PGpioSimpleSetValue (57, 0);

   

/******************/
/* Configure GPIO */
/******************/
 

[Anonymous]

Hi Ken,

       

This piece of code is not needed for GPIF II master state machine implementation.

   

I could not find this piece of code in the project files attached to "Designing a GPIF™ II Master Interface" application note.

   

Please use the latest files that are attached to this application.

       

Thanks,

   

Sai Krishna.

[Anonymous]

I am using this project now and I would like to be clock master.  I have the attached GPIF Prject configured that I am clock master and I am sending PCLK out and the GPIF project  just sends the data out the port with no handshaking required.  This is just very simple project to send the data out to help learn the GPIF libraries.  I dont see any code on the C files that "Enable PCLK" so I think this is done in the GPIF configuration.

       

However, when I use the created GPIF files with this project, I dont see any clocks on the mictors on the board.  I am looking at all of the mictor signals on both mictors. The only thing I see are the UART messages.  I was thinking that since I am Clock master I would be getting a continuous GPIF clock out GPIO16 or PCLK.  What am i doing wrong?

       

Ken