We are sorry to say that currently we don't have any reference schematic design for NoBL SRAM. However, since the part operates at comparatively low frequency, we can connect it pin to pin (from FPGA to Memory). But we always recommend our customers to perform SI Simulations for the same and check if the signals look good with or without terminations.
If you would like to add termination resistors, then it is typically recommended to use series termination or pull-up (pull-down) termination on the clocks and the data signals, and optionally on the address and the control signals depending on how the signal integrity looks. Please check this link for more details:
One thing which you might have to take care would be the decoupling capacitors to be used in the design. I think the following article would help you with the Design of Decoupling Capacitors
We can also review your schematic once you are done with the same.