IOC.2 is polled here to see if FPGA configuration is complete.
It is not enough if you just poll for IOC&0x02, because IOC.2 pin is input to FX2 and output of FPGA and its state can be anything during the configuration (it can go high during configuration)
So a dummy condition was added just to check if it trasitions from low to high.
That is the reason following code is used
In that code, firstly check low then chek high.
During check low to check high, IOC have to change value 0x02.
But i don't understand what make IOC value to 0x02?
If you say that's FPGA, but my answer is NO
In detail, done is need to reset from fpga. Also reset is made by sync from fx2lp's.
So what i'm saying is, that code does not make sense.
I will explain you the functionality of firmware here.
Initially the Slave FIFO interface of FX2LP is configured to use its internal clock. If you configure it to work on the external clock then external clock source must be present before the firmware sets IFCONFIG.7 = 0. But in our case, the FPGA connected to FX2LP is not programmed yet. So we need to configure FX2LP's Slave FIFO interface to work on internal clock till FPGA is ready to supply the clock.
FX2LP firmware drives the PA1 GPIO to high so that you can program the FPGA connected to FX2LP over JTAG. Once the FPGA is programmed then we are changing the configuration of Slave FIFO (using IFCONFIG register) to use the external clock supplied from the FPGA.
We are using PC1 for this purpose. "done_d" signal (G11 on ztex hardware board) on the FPGA is configured as output signal and this is tied to PC1 on the FX2LP. FPGA is driving this signal to LOW initially and changing its value to HIGH after 10 clock cycles. FX2LP firmware is waiting for this condition to happen before re-configuring the Slave FIFO to accept the clock from FPGA. Once this is done, FPGA
I hope my explanation is clear to you. Please let me know if you have any questions on this topic.
(IOC &0x02) mean pin 2 of port C of FX2LP which is connected to 'done' pin of FPGA
In the verilog code of slave_fifo_stream_in~.v,
i can see as below
assign reset_n = sync &lock;
what is initial value of sync?
And when is sync transition?
I have some query as belowMy question as below1. done_d need wait_s, wait_s need reset_n from high to low.But there is not reset_n transition.
I see your point here.
You are talking about the following statement. right?
assign reset_n = sync & lock;Can you please change that assignment statement to as shown below:assign reset_n = lock;Thanks,Sai Krishna.