2 Replies Latest reply on Oct 5, 2013 2:22 PM by user_14586677

    DelSig Considerations

    user_14586677

      When using the DelSig at high resolution there are many considerations

         

      that come into play. A good example is the design consideration doing a load

         

      cell over large dynamic range.

         

       

         

      If we use DelSig at 20 bits, 1.024 Vref, range +/- 1.024, then 1 LSB = ~ 2 uV.

         

       

         

      If we look at lead free solder, the seebeck coefiicient is ~ 2 uV / 0K (consult solder

         

      datasheet). So for a 50 C rise in design, each transition junction on the board yields

         

      50 LSBs of error. If in diff mode, and junction count equal on each input, then this

         

      gets eliminated. You can have an imbalance of junctions in chained ground layouts,

         

      signal path nodes not present in ground path, etc., thats when your problems multiply.

         

      Diff mode and layout practices ways of handling this.

         

       

         

      Also PSRR in any signal path components, like an OpAmp, can add to this. For

         

      example if PSRR is 60 db, Vdd changes by 100 mV, then that yields OpAmp output

         

      change of 100 uV, another 150 LSBs of error.

         

       

         

      Noise, CMRR, thermoelectric effects, INL, DNL, additionally all have to be considered.

         

       

         

      Just some of many considerations in attached ap notes, look at AN280 first.

         

       

         

      Regards, Dana.