Hi squarez I couldn't find any API for change the clock phase,
And no control register for determine the clock phase.
And no clue from detail block diagram of SPI module.
Is it mean can't change the phase at the run time.
One idea comes up, that use Inverter logic at the MOSI line.
To use dedicated wiring to each device, FRAM and MDAC.
But, I couldn't know that the detail clock phase just meet with your devices.
Correct "MOSI line" to "SCLK line"
Didn't know why because clock phase has four different pattern.
You could think of reverting the clock polarity together with the appropiate SS-signal and a bit of logic (XOR). I did not have a look into the sources yet, but parameters that cannot be changed by an API usually are hard-coded using #ifs.
I think best is to rais a case to Cypress.
The SPIM component has been designed in such a way that it generates the corresponding verilog code depending on the mode you choose in the dialog box. Hence, the mode option is not run-time configurable. So, if you would want the component to work in 1 of 2 modes, whose selection you might change during run-time, it would be better if you use 2 separate SPIM modules: one configured to mode 0 and the other configured to mode 2. You can use a Digital Multiplexer to choose which set of SS, MOSI and MISO lines are to be connected to the IO pins.
The reason behind why I am recommending this option instead of modifying the SPIM block internally is because, in either case, the result would turn out to occupy same number of digital resources (datapaths and PLDs) and hence you will not find any significant difference between the two.
I hope this helps.
Thanks and Regards,