3 Replies Latest reply on Oct 28, 2013 6:44 PM by eyal.niv

    FX2LP synchronous FIFO setup times?

    patrick.allison

      Hi all:

         

      According to the FX2LP's datasheet, the SLRD and SLWR setup and hold times are virtually impossible to meet at 48 MHz: the setup time is listed as 18.7 ns with a minimum hold time of 0 ns for SLRD, and 18.1 ns with a minimum hold time of 0 ns for SLWR. With a 20.83 ns clock, this means that the data only has 2.13 and 2.73 ns to change, over all process/voltages/temperature. For virtually any FPGA design this is essentially impossible to meet.

         

      What I don't understand is that Cypress has an FPGA FX2 slave FIFO design published at AN61345:

         

      http://www.cypress.com/?rID=43046

         

      and that design explicitly does *not* meet the timing requirements in the datasheet. Not even particularly close: the timign report loopback/Loopback_verilog/fpga_master.twr gives:

         

      Clock clk to Pad
      ------------+------------+------------------+--------+
                  | clk (edge) |                  | Clock  |
      Destination |   to PAD   |Internal Clock(s) | Phase  |
      ------------+------------+------------------+--------+
      faddr<1>    |    7.873(R)|clk_BUFGP         |   0.000|
      fdata<0>    |    9.839(R)|clk_BUFGP         |   0.000|
      fdata<1>    |   10.479(R)|clk_BUFGP         |   0.000|
      fdata<2>    |    9.943(R)|clk_BUFGP         |   0.000|
      fdata<3>    |   10.487(R)|clk_BUFGP         |   0.000|
      fdata<4>    |   10.263(R)|clk_BUFGP         |   0.000|
      fdata<5>    |   10.275(R)|clk_BUFGP         |   0.000|
      fdata<6>    |   10.765(R)|clk_BUFGP         |   0.000|
      fdata<7>    |    8.748(R)|clk_BUFGP         |   0.000|
      gstate<0>   |    8.812(R)|clk_BUFGP         |   0.000|
      gstate<1>   |    8.851(R)|clk_BUFGP         |   0.000|
      gstate<2>   |    7.434(R)|clk_BUFGP         |   0.000|
      sloe        |    8.575(R)|clk_BUFGP         |   0.000|
      slrd        |    7.768(R)|clk_BUFGP         |   0.000|
      slwr        |    8.581(R)|clk_BUFGP         |   0.000|
      ------------+------------+------------------+--------+

         

      You can see here that SLRD and SLWR have a clock-to-out time of ~8 ns, which implies, with a 20.83 ns IFCLK (which the firmware included with AN61345 uses) a setup time of ~13 ns, which is about 5ns *shorter* than the time specified in the FX2LP datasheet.

         

      Does anyone have any idea what the real setup time requirements are for SLRD/SLWR for the FX2LP, or is it just impossible to run IFCLK at 48 MHz over all operating conditions?