1 Reply Latest reply on Nov 21, 2013 12:27 PM by PriteshM_61




      I'm currently looking for a SRAM for my FPGA based design. The CY7C1462AV33 is a NoBL, pipelined 18x SRAM that supports up to 250MHz (i would like to use 200MHz). I have a few questions regarding that SRAM.


      According to: http://www.cypress.com/?id=4&rID=30080 a single write cycle would take 2 clock cycle. Would a linear 4x writeburst take 5 clock cycle or also 2 cycle for every single write?


      Since I'm using a FPGA to interface the SRAM, i want to spare as many I/O pins as possible. Is it possible to connect /CE1 and /CE3 to ground and just use CE2 as HIGH active CE?

        • 1. Re: CY7C1462AV33





          --> For example, If you start the first write at clock X then your write data will be presented on data bus at X+2 clock. In the linear write operation, the write data will be presented at every clock cycle so with respect to clock X, the write operation will be finished by clock X+5 (write data will be on X+2, X+3, X+4 & X+5) but if you break down this linear write operation in to the single write operation then with respect to clock X+1 write operation, your second write will happened on clock X+3, similarly with respect to clock X+2, the write data will be presented on clock X+4.




          So, single write operation always takes 2 clock cycles but linear 4x write burst will take 5 clock cycles to write with respect to the first write command. Please refer Figure 4 of the datasheet (http://www.cypress.com/?docID=40032), you will get an clear idea from first three write operations.   




           --> Yes, you can connect /CE1 and /CE3 to ground and use CE2 for chip enable because chip is enabled when /CE1 is LOW, CE2 is HIGH and /CE3 is LOW.


          And Chip is disabled when /CE1 is HIGH or CE2 is LOW or /CE3 is HIGH.


          So you can use CE2 as your chip enable signal.