2 Replies Latest reply on Aug 31, 2013 1:09 AM by tang.pu

    slave fifo partial flag

    tang.pu
              Like what the AN65974 slavefifo sample do in the gpif design, I use 4 partial flag to indicate 4 dedicated socket, active low then like its firmware, I configure the watermark CyU3PgpifSocketConfigure (0, PIB_SOCKET_0, 3, CyFalse, 1); CyU3PgpifSocketConfigure (1, PIB_SOCKET_1, 3, CyFalse, 1); CyU3PgpifSocketConfigure (2, PIB_SOCKET_2, 4, CyFalse, 1); CyU3PgpifSocketConfigure (3, PIB_SOCKET_3, 4, CyFalse, 1); 0,1 is consumer socket, 2,3 is producer socket. Before starting to transfer, the 4 flag is supposed to be 0,1 high and 2,3 low, which means 0,1 cannot be read while 2,3 can be written by fpga but actually its 0,1 low, 2,3 low which break the fpga logic please help, thanks   
        • 1. Re: slave fifo partial flag
          tang.pu
                  Like what the AN65974 slavefifo sample do in the gpif design, I use 4 partial flag to indicate 4 dedicated socket, active low then like its firmware, I configure the watermark CyU3PgpifSocketConfigure (0, PIB_SOCKET_0, 3, CyFalse, 1); CyU3PgpifSocketConfigure (1, PIB_SOCKET_1, 3, CyFalse, 1); CyU3PgpifSocketConfigure (2, PIB_SOCKET_2, 4, CyFalse, 1); CyU3PgpifSocketConfigure (3, PIB_SOCKET_3, 4, CyFalse, 1); 0,1 is consumer socket, 2,3 is producer socket. Before starting to transfer, the 4 flag is supposed to be 0,1 high and 2,3 low, which means 0,1 cannot be read while 2,3 can be written by fpga but actually its 0,1 low, 2,3 low which break the fpga logic please help, thanks   
          • 2. Re: slave fifo partial flag
            tang.pu
                    i don't know how to handle the typesetting though I insert many carriage return, I have to edit it perfect in a txt uploaded, please check it, thanks