For FRAM, /OE and /WE being HIGH, if CS goes low and an address change happens, will this internally be considered as a read as far as endurance is concerned?
Each read and write causes one endurance cycle for the device.Even with /OE and /WE high, the device will internally start a read cycle at every falling /CE. The /OE pin only influences when the output pads begin to drive. It does not qualify the Read cycle. So this will be internally treated as a read cycle and will be cause one endurance cycle for the device.