For Async SRAM, there are two timing parameters assosiated with read cycle, tDOE and tACE . tDOEis the maximum time from/OE Low to data valid and tACEis the maximum time from /CE Low to data valid on the bus during a read operation.
a) If you assert /CE at least (tACE - tDOE) time ahead of /OE , data will come at tDOE from the falling edge of /OE.
b) If you assert both /CE and /OE together, it will take tACE time from /CE or /OE falling edge for valid data to come on the bus.
Hope this clarifies the difference between the two parameters.