11 Replies Latest reply on Dec 16, 2013 1:13 PM by user_14586677

    Delta Sigma ADC very noisy at the top end of its range

    user_62720120

      Hi,

         

       

         

      I'm trying to work out why my delta sigma ADC seems to be very noisy towards the top end of its range (3000 / 4095). My ADC is set up as follows: Single Sample, 12-bits, 40000SPS, Single ended input mode, Vsssa to 1.25v, Buffer Gain 1, Rail to Rail, Vref = Vdda/4. I have 12 PSoC pins connected to an analogue multiplexer, and am using a simple RC filter on each input pin.

         

      When the input voltages are low (around 500/4095) there is very little noise, sometimes it can be as low as 1.5 LSB. But around 2000/4095, I can see around 6-10 LSB. By 3000/4095, I can see about 20LSB noise!

         

      I'm using separate analogue and digital linear regulators with ferrite bead filters. I have a continuous ground plane under the PSoC. I have also read the several application notes on achieving good ADC performance, and I believe I am following all of the advice.

         

      Is this amount of noise to be expected, or am I doing something wrong?

         

       

         

      Hugo

        • 1. Re: Delta Sigma ADC very noisy at the top end of its range
          user_1377889

          With the given setup my ADC (v 3.0) is only able to give 20,000 SPS. Did you try to bypass the reference at pins ü0.3 or p3.2?

             

           

             

          Bob

          • 2. Re: Delta Sigma ADC very noisy at the top end of its range
            user_62720120

            Hi Bob,

               

             

               

             Argh! I tried to attach a .zip containing screenshots of the noise, and the ADC config dialog, but it doesn't seem to have attached. Now I'll have to wait until I get back into work on Monday to post the images of the noise, but here's the ADC config.

               

            Hugo

            • 3. Re: Delta Sigma ADC very noisy at the top end of its range
              user_62720120

               And here's the ADC input circuit. I've just drawn in one of the input circuits, but all 12 are the same. The voltage across the potentiometer is 5v, and the 33k resistor divider ensures that the maximum ADC input voltage is less than 1.25v.

                 

               

                 

              Hugo

              • 4. Re: Delta Sigma ADC very noisy at the top end of its range
                user_14586677

                @Bob, odd, I can do 192K SPS on 12 bits and ref settings.

                   

                 

                   

                In terms of noise, since reference is a voltage R derived from Vdd, which

                   

                is pretty noisy, Bobs suggestion almost mandatory. If you put your scope

                   

                on infinite persistance, look at Vdd rail, you will get pk-pk noise.  Very typical

                   

                to see 200 mV of noise. 12 bits with your ref settings implies 1 LSB =

                   

                .6 mV, so Vdd noise would be 50 mV at ref, that  would be 50 / .6 =~ 83 lsbs.

                   

                 

                   

                I would suggest you tie all mux inputs to a single ref level, well bypassed, say

                   

                half scale, and do a simple test for pk-pk noise on each channel. That will help

                   

                you look at layout noise.

                   

                 

                   

                Also allow settling time for the mux when swicthing channels. You might also

                   

                try continuous conversion mode just to see if you get better/worse results.

                   

                 

                   

                Use polymer tantalums for bulk caps, they have ~ 2 x better f vs ESR curves than

                   

                traditional tants.

                   

                 

                   

                Regards, Dana.

                • 5. Re: Delta Sigma ADC very noisy at the top end of its range
                  user_62720120

                  Dana,

                     

                   

                     

                  The ref is Vdda, not Vddd, which I assume doesn't contain switching noise. Both Vddd and Vdda have their own 5v linear regulators with input ferrite filters, so Vdda should be really quiet.

                     

                   

                     

                  Unfortunately, I don't have any spare PSoC pins in my design, I'm using every single one. So I can't use p0.3 or p3.2 for bypass. I'll try adding a little more settling time on the MUX, and I'll see if continuous conversion is any better.

                     

                   

                     

                  Generally, should I expect better noise performance than this?

                     

                   

                     

                  Hugo

                  • 6. Re: Delta Sigma ADC very noisy at the top end of its range
                    user_62720120

                     Here are the waveforms showing the noise level at different input levels.

                       

                    Hugo

                    • 7. Re: Delta Sigma ADC very noisy at the top end of its range
                      user_14586677

                      In your screenshot of ADC config you show ref as Vdda/4 ?

                         

                       

                         

                      I looked for bandgap noise specs, could not find any. You might, as a test,

                         

                      digitize the reference to see if you can determine nosie source. Also keep

                         

                      in mind a bandgap's design does not inherently make it immune to switching

                         

                      noise.

                         

                       

                         

                      Averaging readings will certainly help.

                         

                       

                         

                      Regards, Dana.

                      • 8. Re: Delta Sigma ADC very noisy at the top end of its range
                        user_78878863

                        The noise specs are in the component data sheet for the DeltaSigma-ADC, figure 4:

                           

                         

                           

                        So without bypass cap we are talking about 20db more noise. The DS also recommend at least 10nF bypass cap for 10 bit. So it looks like you cannot expect better performance than you are seeing already.

                           

                         

                           

                        @Dana: single-sample mode, as used by RocketMagnet, allows only up to 40ksps in 12 bit. For 192ksps you would need continuous sample mode. (And this rate gets then divided by the buffer gain, maybe thats what bob has seen additionally)

                        • 9. Re: Delta Sigma ADC very noisy at the top end of its range
                          user_14586677

                          I was looking at wrong mode, regarding SPS, thanks for the correction.

                             

                           

                             

                          Ref noise probably done with no other UDB's in operation, another consideration.

                             

                           

                             

                          Regards, Dana.

                          • 10. Re: Delta Sigma ADC very noisy at the top end of its range
                            user_62720120

                             I'm slightly confused about the ref.

                               

                             

                               

                            I am using Vdda/4 as the ref, not the 1.024v bandgap. Shouldn't switching noise be very low in Vdda? I have 100nF at the Vdda pin, preceded by a linear regulator with its own 2uF cap, preceded by a ferrite bead.

                               

                             

                               

                            Looking at the Vdda pin with a scope, I can see that the noise is within ±4mv (completely within 2 divisions at 2mv/div). So, I'm finding it very hard to believe that this noise problem is due to the reference voltage.

                               

                             

                               

                            Hugo

                            • 11. Re: Delta Sigma ADC very noisy at the top end of its range
                              user_14586677

                              Sorry if I was confusing.

                                 

                               

                                 

                              If Vdda is 3.3V, running 12 bits, 1 LSB =~ .8 mV. So if you are seeing 8 mV pk-pk noise,

                                 

                              thats same as Noise = ( 1 LSB / .8 mV ) x 8 mV = 10 LSBs Vdda refered or 2.5 at ADC

                                 

                              Vref input.. So you are correct, that is not dominate contributor. But it does contribute RMS

                                 

                              fashion. Also keep in mind when using scope its performance at low signal levels typically

                                 

                              not same as advertised BW. Check its  noise level contribution and its BW on high

                                 

                              sensitivity range(s).

                                 

                               

                                 

                              Vdda will have some switching noise, its not totally isolated, that would be an additional

                                 

                              RMS noise term to add. The grounds have to meet somewhere, and depending on how

                                 

                              much ground noise from all signals/power domains Vssa and Vssd currents will aggravate

                                 

                              the problem. Lastly examine external linear reg graphs of noise BW, you will see its ability

                                 

                              to reject noise at high f also drops dramatically.

                                 

                               

                                 

                              For accurate scope reading use infinite persitance if it is DSO, you will get more accurate results

                                 

                              then just trying to use trigger level on analog scope to determine where peak lies.

                                 

                               

                                 

                              Regards, Dana.