The MPN you have mentioned (CYF0018V) is a single queue 18Meg HDFIFO device which has a single DVal signal. The device supports a read latency of 4.
In the waveform you have provided, after REN is enabled, clock cycle 1 is when the HDFIFO will register the first read request. With respect to this clock edge, "DVal#2" in the waveform you have provided, is the correct interpretation of device operation.
Please let us know if any further clarification is required in this regard.
Thanks & Regards,
Adithi Murthy Perepu