I do not see in module datasheet or device datadsheet or TRM
any discussion. If you are using Hysterisis I suspect you may be
seeing +fdbk R's used to develop fdbk.
File a case at -
“Create a Case”
Or use DelSig, and a sampling R to measure the current going into Comparator,
that might be instructive. Are you using Hysteresis ?
If you file a case let forum know what answer was.
In the CY8C38 family data sheet, the (typical) input current is specified as 2 nA, or 14nA for SIO pins. It might be higher, but not _that_ much.
Are you sure you have the pins really configured as analog high-Z?
I am not sure of what the applicability of the SIO pin input leakage is to this
Pins being used are GPIO configed as analog, connected to a comparator,
unless I misunderstood something...which wouldn't be the first time.
My apologies, I see you might have been think SIO comparator functionality
was being used -
No, I meant to calculate the input impedance from the current flowing in the pin (2 nA would, at 5 V, result in an input resistance of 2.5 GigaOhm). This is the only specification I can find for that value. The Comparator compoinent data sheet states that the comparator is implemented as trimmer differential amplifier, and hysteresis is not handled by a feedback resistor it seems.
So I guess the problem doesn't stem from the input impedance.
Pretty much all comparators implemented by using high gain diff amp,
and trimmed as it states. It does say offsetting currents are added to
input stage to generate Hysteresis, that could be done with I source or
simple R's, either way that would affect Zin, or so I think. Thats why a
case needs to be filed, we are fishing with guesses at this point.