In UART datasheet on page 46 you can see in the timing-diagrams that rts_n is directly coupled to FIFO full and it will be de-asserted as soon as there is room in the buffer for at least one byte.
Since you are in PSoC5 world it is easy to gate the rts_n signal with some logic and a control register to meet the timing with the needs of your sending device.
Thanks for the note, Bob.
What I did was to gate the signal like you suggeste, but controlled by software; when the buffer gets almost full, I tell the sender to stop.
This works great, but after some more playing it appears that I was having another problem that was the true source of difficulty, and maybe I don't need the software control.
However, it works so nice the way it is, I am disinclined to change it... ;-)
Thank you for your feedback, you are always welcome.