By the way, it is not obvious by my code above how I know that either the CPU has stalled or interrupts are being disabled. There is an interrupt every 250usec in which I toggle an output. This stops for around 10msec when this call is made in the non-isr context.
Cypress confirmed that the TRM is incorrect. The cache and SPC cannot access Flash at the same time regardless of array or row... Be careful if you are using flash for storage of anything other than code using the bootloader.