6 Replies Latest reply on Feb 4, 2014 3:17 AM by JoMe_264151

    Duty Cycle Varies with Frequency of Write

      Hi, I am new to PSoC programming, and I have encountered some confusing
      behavior. I have a PSoC5 LP device, and I'm trying to develop a parallel
      interface using a port on the device. I began testing my write speed by simply
      writing two alternating values on the port: specifically, I wrote 0x40 and 0x01
      to the correct register for P6. These values will alternate driving P6_6 high
      and P6_0 high. That is, while P6_6 is high, P6_0 is low, and vice versa. If I do
      this at a rather slow speed, I get a nice waveform that you'd expect from these
      pins, What is strange is that whenever I try to optimize the bus speed and clock
      speed to achieve an overall frequency somewhere above ~2MHz, I get a somewhat
      deformed duty cycle on both pins. So where before I'd have about a 50% duty
      cycle on both pins, now I have about a 33% duty cycle on one pin, and a 66% duty
      cycle on the other. Here are some images of the waveforms at the slow and high
      speeds, respectively:





        • 1. Re: Duty Cycle Varies with Frequency of Write

          Are you writing directly to port DR register ?








          http://www.cypress.com/?rID=57571      AN72382     Page 10








          Regards, Dana.

          • 2. Re: Duty Cycle Varies with Frequency of Write

            In this case of tight programming the simple branch instruction at the end of the loop you programmed will consume some time wihch will be spent in the last-written pin state. This could be the cause of the asymetric duty-cycle.


            There have been several tries to find out the maximum speed a pin could be toggled by software but it turned out that for the most cases the results were for curiosity only. Quite different from a PIC or other microcontrollers PSoCs contain some hardware that can do this job better and at higher frequencies. So when you connect a timer with a divisor of 2 to a pin and feed the timer with a 48 MHz clock you'll see a 24MHz output on the pin. Even this fast signal could be modified with the internal hardware, for instance you may program a "Digital Burst" which, when triggered issues a given number of clock cycles out of the pin. And so on.... Fascinating world of PSoCs!!!




            Happy coding



            • 3. Re: Duty Cycle Varies with Frequency of Write

              Thank you very much for your helpful replies, and sorry for the triple post... I had a look at the disassembled code and it indeed shows the branch instruction,  which occurs only after the second toggle. What Bob has described looks to be  exactly what is happening.  




              To give a better frame of reference for the project I'm working on, I'll explain a little more about it in detail. I am working on creating a flash chip driver in order to transfer data from RAM on the microcontroller to the flash chip. I want to be able to transfer 8 bits in parallel repeatedly over a port as fast as possible. I have some basic ideas about what to do, but, being new to PSoC, I'm not sure of what might be the idiomatic way to go about the operation. Specifically, I've considered using DMA to write to a control register for the port, and after the DMA transfer is complete for a byte, send the correct signal to the flash chip to signal end-of-write for that byte.  


              If you guys were trying to do this, what would you try first, or have you done something similar before? If so, I would really appreciate any help that you can offer.

              • 4. Re: Duty Cycle Varies with Frequency of Write

                Take a look at the EMIF component, that may be one approach.




                Regards, Dana.




                • 5. Re: Duty Cycle Varies with Frequency of Write

                  DMA should give high transfer rate but what is the mininum transfer rate? And what is the size of data needs to be store per transaction and total? Would using EEPROM be OK as this would not need to have the enable/disable write instruction, but EEPROM would be slower. Don't forget flash needs to be erase before wirting, was that a problem when you need to overwrite the old records?

                  • 6. Re: Duty Cycle Varies with Frequency of Write

                    Cypress usually says: "PSoCs can. MPUs don't"


                    The ARM core within a PSoC5 is clocked at only 67MHz. That is not much compared to the ARMs within your cellphone. What makes the PSoCs such a mighty chip is the amount of routable internal hardware that may run at the same frequency without any intervention of the CPU. Suported by DMA you may transfer data without use of the CPU, too.


                    And this is not the end: Within a PSoC are up to 24 UDBs consisting of an 8-bit programmable ALU, two FIFOs each 4 levels deep and a Hardware Description Language (HDL) named VeriLog to access all that


                    So the way to "think" PSoC is: Use the schematic-editor and put as much into hardware as you can, then just control the hardware with the CPU.