Getting Started with I2C in PSoC1
The Cypress PSoC 1 product family offers several choices for implementing I2C in a design. These choices come in the form of user modules (UMs) that are found in the PSoC Designer IDE. The I2C communication itself is handled by a dedicated I2C hardware (HW) block which removes much of the I2C processing burden from the CPU, freeing the CPU to do more important real-time tasks.
Figure 1: I2C Hardware Block
The HW block is a serial to parallel processor designed to interface the PSoC 1 to an I2C bus. The HW block takes the burden off the CPU by providing support for HW detection of I2C status and generation of I2C signals.
The first user module to consider is the EzI2Cs UM. The EzI2Cs UM operates exclusively as a slave; there is no master version of EzI2C. The EzI2Cs UM is a firmware layer on top of the I2C hardware block. It requires minimal user knowledge of how the I2C bus works by allowing you to setup a data structure in user code, and exposing that structure to the I2C master. All I2C transactions happen in the background through interrupts. You need not worry about any of the I2C functionality once the user module is started in the main code.
This user module is a firmware layer on top of the I2C HW bloc and can be used as a slave, master, or multi-master slave. Unlike EzI2Cs, this user module requires more designer interaction. Status bits must be checked to see if an I2C transaction occurred. The main firmware also needs to check for error conditions on a transaction. Finally, user code must clear the status bits that are set.
For a detailed overview of the I2C block in PSoC1 and example usage of the user modules described above, please refer application note AN50987 - Getting Started with I2C in PSoC® 1.