If you have no realtime needs, your suggestion might work. Having the same filter configuration for all channels (or at least the two pairs) will help.
The implementation of this solution might be easier with DMA, in that case you can even have it more or less automatically (by doing ping-pong-DMA between two buffers).
Certainly using the DFB Editor and assembler one could easily imagine
multiple IIR or FIR solutions exceeding 2 filter limitations. Basically
create from scratch your own DFB.
Or using Verilog and the MAC in the DFB.
All depends of course on required filter performance and sampling rates
associated with filter requirements.
From an analog perspective the TIA has effectivley programmable bandwidth.
There are techniques of using the 1 pole comped OpAmp for filtering appications
with just resistors. Just google "capacitorless OpAmp Filters".
HLI and Dana,
Sorry for not responding sooner, last week was very hectic for me!
My exact timing contstraints have yet to be figured out, but as fast as performance as possible would be desired, so I think I will examine using the DFB as a DSP engine along with some judiciouse use of DMA.