6 Replies Latest reply on Mar 7, 2014 7:49 PM by xl.xl

    slaveFIFO  ADconvert  FPGA

    xl.xl

      68013 works in slaveFIFO mode, transefering data produced by AD converter to PC. Between them , I uses a FPGA to buffer data.

         

      And the endpoint in the usb is 512bytes, quadruple. My result is not good and there is some points are wrong. I don't kown why. 

         

       

         

       

         

       

        • 1. Re: slaveFIFO  ADconvert  FPGA
          vavc

          Hi

             

          It seems that some of the data is missing in between. Could you please share the firmware? Are you continously sending the data from FPGA to FX2LP? or checking the full flag before sending the data?

             

           

             

          Regards,

             

          Vikas.

          • 2. Re: slaveFIFO  ADconvert  FPGA
            xl.xl

             yes.

               

            I have checked the full flag before sending the data.

            • 3. Re: slaveFIFO  ADconvert  FPGA
              vavc

               Hi 

                 

               

                 

              Please share the firmware and schematics. 

                 

               

                 

              Regards,

                 

              Vikas.

              • 4. Re: slaveFIFO  ADconvert  FPGA
                xl.xl

                 void TD_Init( void )

                   

                { // Called once at startup

                   

                 

                   

                  CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT

                   

                //  FIFOPINPOLAR |= 0x03;

                   

                 

                   

                  PINFLAGSAB = 0x08; // FLAGA - EP6FF

                   

                  SYNCDELAY;

                   

                  PINFLAGSCD = 0xE0; // FLAGD - EP2EF

                   

                  SYNCDELAY;

                   

                  PORTACFG |= 0x80;

                   

                    SYNCDELAY;

                   

                  IFCONFIG = 0xE3; // for async? for sync?

                   

                  SYNCDELAY;

                   

                 

                   

                 CPUCS |= 0x02;

                   

                 

                   

                  // IFCLKSRC=1   , FIFOs executes on internal clk source 

                   

                  // xMHz=1       , 48MHz operation

                   

                  // IFCLKOE=1    ,Drive IFCLK pin signal at 48MHz

                   

                  // IFCLKPOL=0   , Don't invert IFCLK pin signal from internal clk

                   

                  // ASYNC=0      , master samples synchronous

                   

                  // GSTATE=0     , Don't drive GPIF states out on PORTE[2:0], debug WF

                   

                  // IFCFG[1:0]=11, FX2 in slave FIFO mode

                   

                 

                   

                 

                   

                  // Registers which require a synchronization delay, see section 15.14

                   

                  // FIFORESET        FIFOPINPOLAR

                   

                  // INPKTEND         OUTPKTEND

                   

                  // EPxBCH:L         REVCTL

                   

                  // GPIFTCB3         GPIFTCB2

                   

                  // GPIFTCB1         GPIFTCB0

                   

                  // EPxFIFOPFH:L     EPxAUTOINLENH:L

                   

                  // EPxFIFOCFG       EPxGPIFFLGSEL

                   

                  // PINFLAGSxx       EPxFIFOIRQ

                   

                  // EPxFIFOIE        GPIFIRQ

                   

                  // GPIFIE           GPIFADRH:L

                   

                  // UDMACRCH:L       EPxGPIFTRIG

                   

                  // GPIFTRIG

                   

                  

                   

                  // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...

                   

                  //      ...these have been replaced by GPIFTC[B3:B0] registers

                   

                 

                   

                 

                   

                  

                   

                 

                   

                 

                   

                  // EP4 and EP8 are not used in this implementation...

                   

                                   

                   

                  EP2CFG = 0xA0;                //out 512 bytes, 4x, bulk

                   

                  SYNCDELAY;                    

                   

                  EP6CFG = 0xE2;                // in 512 bytes, 4x, bulk

                   

                  SYNCDELAY;              

                   

                  EP4CFG = 0x02;                //clear valid bit

                   

                  SYNCDELAY;                     

                   

                  EP8CFG = 0x02;                //clear valid bit

                   

                  SYNCDELAY;   

                   

                 

                   

                  SYNCDELAY;

                   

                  FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions

                   

                  SYNCDELAY;                    // see TRM section 15.14

                   

                  FIFORESET = 0x02;             // reset, FIFO 2

                   

                  SYNCDELAY;                    // 

                   

                  FIFORESET = 0x04;             // reset, FIFO 4

                   

                  SYNCDELAY;                    // 

                   

                  FIFORESET = 0x06;             // reset, FIFO 6

                   

                  SYNCDELAY;                    // 

                   

                  FIFORESET = 0x08;             // reset, FIFO 8

                   

                  SYNCDELAY;                    // 

                   

                  FIFORESET = 0x00;             // deactivate NAK-ALL

                   

                 

                   

                 

                   

                  // handle the case where we were already in AUTO mode...

                   

                  // ...for example: back to back firmware downloads...

                   

                  SYNCDELAY;                    // 

                   

                  EP2FIFOCFG = 0x00;            // AUTOOUT=0, WORDWIDE=1

                   

                  

                   

                  // core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's

                   

                  

                   

                  SYNCDELAY;                    // 

                   

                  EP2FIFOCFG = 0x11;            // AUTOOUT=1, WORDWIDE=1

                   

                  

                   

                  SYNCDELAY;                    // 

                   

                  EP6FIFOCFG = 0x0D;            // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1

                   

                 

                   

                  SYNCDELAY;

                   

                 

                   

                }

                   

                 

                   

                 

                   

                Above is the firmware . 

                   

                In PC, I use "XferData"  functon to acquire data. And one point needs two bytes. 

                • 5. Re: slaveFIFO  ADconvert  FPGA
                  vavc

                   HI 

                     

                   

                     

                  Please probe the EP6 full flag during the data transmission.Might be because of buffer overflow, some of the data is missing. Stop the data transmission from FPGA if the FULL FLAG is asserted.

                     

                   

                     

                   

                     

                  Regards,

                     

                  Vikas.

                  • 6. Re: slaveFIFO  ADconvert  FPGA
                    xl.xl

                     The wrong points appear regularly. There are some wrong points every 525 points.

                       

                    And these wrong points are not random. Their values are in the sine curve. But they are not in the right sequence.

                       

                    These wrong points should be in the position ahead the wrong position 525 points.