2 Replies Latest reply on Mar 14, 2014 2:50 AM by user_246598725

    is it possible to create a gated clock output?

              Hi, one of the PSoC4 limitations is that it's not possible to use a clock signal for any other purpose than clocking a component. I need a gated clock output for my component. I know that the usual way would be to use a clock two times faster than needed, but I wonder if it's possible by another way. I tried to implement a "any-edge T-FF" in Verilog, which is "accepted" when compiling the design, but it throws a notice about a combinational loop. I haven't tested yet if this really works, I first want to figure out which is the better way. If I have to use a two times faster clock, how is it implemented in the component? Currently I've a state machine which reacts on every clock pulse, but if the above applies, my component must only react on every 2nd clock pulse. Regards, Ralf